PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 122

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
12.6
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES registers. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
TABLE 12-2:
DS30487C-page 120
0Bh, 8Bh
10Bh,
18Bh
0Ch
8Ch
1Eh
9Eh
1Fh
9Fh
9Bh
05h
05h, 106h PORTB
85h
86h, 186h TRISB
Legend:
Note 1:
Address
Note:
2:
3:
A/D Operation During Sleep
INTCON
PIR1
PIE1
ADRESH
ADRESL
ADCON0
ADCON1
ANSEL
PORTA
(PIC16F87)
(PIC16F88)
(PIC16F87)
(PIC16F88)
TRISA
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
PIC16F88 only.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction
instruction that sets the GO/DONE bit.
Name
(2
REGISTERS/BITS ASSOCIATED WITH A/D
(2)
(2)
(2)
(2)
TRISA7 TRISA6 TRISA5
TRISB7 TRISB6
ADCS1 ADCS0
A/D Result Register High Byte
A/D Result Register Low Byte
ADFM
Bit 7
RA7
RB7
GIE
immediately
—
—
—
ADIE
ADCS2
ADIF
ANS6
PEIE
Bit 6
RA6
RB6
(1)
(1)
follows
TMR0IE
TRISB5 TRISB4 TRISB3
VCFG1
CHS2
ANS5
RCIE
RCIF
Bit 5
RA5
RB5
(3)
PORTA Data Direction Register (TRISA<4:0>)
VCFG0
INT0IE
the
CHS1
ANS4
Bit 4
TXIF
TXIE
RA4
RB4
SSPIF
SSPIE
CHS0 GO/DONE
ANS3
RBIE
Bit 3
RA3
RB3
—
12.7
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers
is
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
12.8
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 counter will be reset to zero. Timer1 is reset
to automatically repeat the A/D acquisition period with
minimal
ADRESH:ADRESL to the desired location). The appro-
priate analog input channel must be selected and the
minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), then
the “special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 counter.
TMR0IF
CCP1IF
CCP1IE
TRISB2
not
ANS2
Bit 2
RA2
RB2
—
Effects of a Reset
Use of the CCP Trigger
modified
software
TMR2IE TMR1IE -000 0000 -000 0000
TMR2IF TMR1IF -000 0000 -000 0000
TRISB1 TRISB0
INT0IF
ANS1
Bit 1
RA1
RB1
—
—
for
ADON
ANS0
RBIF
 2005 Microchip Technology Inc.
Bit 0
RA0
RB0
overhead
—
a
Power-on
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
0000 ---- 0000 ----
-111 1111 -111 1111
xxxx 0000
xxx0 0000
xxxx xxxx
00xx xxxx
1111 1111 1111 1111
1111 1111 1111 1111
POR, BOR
Value on
(moving
Reset.
uuuu 0000
uuu0 0000
uuuu uuuu
00uu uuuu
Value on
all other
Resets
The
the