PIC18F26K80-I/SO Microchip Technology Inc., PIC18F26K80-I/SO Datasheet - Page 147
PIC18F26K80-I/SO
Manufacturer Part Number
PIC18F26K80-I/SO
Description
IC, MCU, nanoWatt; 8-bit w/ECAN; Flash, 64KB; 16MIPS; 8-ch, 12-BIT A/D; SOIC-28
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-I/SO
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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8.3
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>) and then set control
bit, RD (EECON1<0>). The data is available after one
instruction cycle, in the EEDATA register. It can be read
after one NOP instruction. EEDATA will hold this value
until another read operation or until it is written to by the
user (during a write operation).
The basic process is shown in
8.4
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. The
sequence in
the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
2011 Microchip Technology Inc.
Reading the Data EEPROM
Memory
Writing to the Data EEPROM
Memory
Example 8-2
must be followed to initiate
Example
8-1.
Preliminary
PIC18F66K80 FAMILY
After a write sequence has been initiated, EECON1,
EEADRH:EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a
previous instruction. Both WR and WREN cannot be
set with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit; EEIF must be cleared by software.
8.5
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
Note:
Write Verify
Self-write
EEPROM memory cannot be done while
running in LP Oscillator (low-power)
mode. Executing a self-write will put the
device into High-Power mode.
execution
DS39977C-page 147
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