PIC18F26K80-I/SO Microchip Technology Inc., PIC18F26K80-I/SO Datasheet - Page 69

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: IC, MCU, nanoWatt; 8-bit w/ECAN; Flash, 64KB; 16MIPS; 8-ch, 12-BIT A/D; SOIC-28
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-I/SO

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

FIGURE 4-1:
FIGURE 4-2:
4.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the LF-INTOSC source, this
mode provides the best power conservation of all the
Run modes, while still executing code. It works well for
user applications which are not highly timing-sensitive
or do not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block – either LF-INTOSC or INTOSC (MF-INTOSC or
HF-INTOSC) – there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. Entering or exiting RC_RUN mode, how-
ever, causes a clock switch delay. Therefore, if the
primary clock source is the internal oscillator block,
using RC_RUN mode is not recommended.
 2011 Microchip Technology Inc.
Peripheral
Note 1: Clock transition typically occurs within 2-4 T
Program
Counter
SOSCI
OSC1
Note1: T
Clock
Clock
RC_RUN MODE
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
Output
2: Clock transition typically occurs within 2-4 T
SOSC
OSC1
Clock
Q1
OST
SCS<1:0> Bits Changed
Q2
= 1024 T
PC
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q3
Q4
OSC
; T
Q1
PLL
Q1
1
= 2 ms (approx). These intervals are not shown to scale.
T
OST (1)
PC
2
Q2
Clock Transition
3
OSC
T
OSTS Bit Set
Q3
PLL (1)
Preliminary
.
OSC
.
(1)
PC + 2
n-1
Q4
PIC18F66K80 FAMILY
This mode is entered by setting the SCS1 bit to ‘1’. To
maintain software compatibility with future devices, it is
recommended that the SCS0 bit also be cleared, even
though the bit is ignored. When the clock source is
switched to the INTOSC multiplexer (see
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
n
Q1
1
Note:
Transition
2
Clock
n-1 n
(2)
Q2
Caution should be used when modifying a
single IRCF bit. At a lower V
possible to select a higher clock speed
than is supportable by that V
device operation may result if the V
F
PC + 2
OSC
Q3
specifications are violated.
Q2
Q4
Q3 Q4
Q1
Q1
PC + 4
Q2
PC + 4
Q2
DS39977C-page 69
Q3
Q3
DD
Figure
. Improper
DD
, it is
4-3),
DD
/