PIC18F26K80-I/SO Microchip Technology Inc., PIC18F26K80-I/SO Datasheet - Page 461

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: IC, MCU, nanoWatt; 8-bit w/ECAN; Flash, 64KB; 16MIPS; 8-ch, 12-BIT A/D; SOIC-28
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-I/SO

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

28.0
The PIC18F66K80 family of devices includes several
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Oscillator Selection
• Resets:
• Interrupts
• Watchdog Timer (WDT) and On-chip Regulator
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in
“Oscillator Configurations”
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F66K80 family of
devices has a Watchdog Timer, which is either perma-
nently enabled via the Configuration bits or software
controlled (if configured as disabled).
The inclusion of an internal RC oscillator (LF-INTOSC)
also provides the additional benefits of a Fail-Safe
Clock Monitor (FSCM) and Two-Speed Start-up. FSCM
provides for background monitoring of the peripheral
clock and automatic switchover in the event of its fail-
ure. Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
 2011 Microchip Technology Inc.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
SPECIAL FEATURES OF THE
CPU
.
Section 3.0
Preliminary
PIC18F66K80 FAMILY
28.1
The Configuration bits can be programmed (read as
‘ 0 ’) or left unprogrammed (read as ‘ 1 ’) to select various
device configurations. These bits are mapped starting
at program memory location, 300000h.
The user will note that address, 300000h, is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
Software programming the Configuration registers is
done in a manner similar to programming the Flash
memory. The WR bit in the EECON1 register starts a
self-timed write to the Configuration register. In normal
operation mode, a TBLWT instruction with the TBLPTR
pointing to the Configuration register sets up the address
and the data for the Configuration register write. Setting
the WR bit starts a long write to the Configuration
register. The Configuration registers are written a byte at
a time. To write or erase a configuration cell, a TBLWT
instruction can write a ‘ 1 ’ or a ‘ 0 ’ into the cell. For
additional details on Flash programming, refer to
Section 7.5 “Writing to Flash Program Memory”
Configuration Bits
DS39977C-page 461
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