ICS1893Y-10LF IDT, Integrated Device Technology Inc, ICS1893Y-10LF Datasheet - Page 4

• Manufacturer Part Number: ICS1893Y-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893Y-10LF; 800-1935-5; ICS1893Y-10LF

ICS1893 Rev C 6/6/00
Section
Chapter 8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.4
ICS1893 Data Sheet - Release
Management Register Set ............................................................................................... 59
Introduction to Management Register Set ............................................................. 60
Management Register Set Outline ......................................................................... 60
Management Register Bit Access .......................................................................... 61
Management Register Bit Default Values .............................................................. 61
Management Register Bit Special Functions ......................................................... 62
Register 0: Control Register ................................................................................... 63
Reset (bit 0.15) ...................................................................................................... 63
Loopback Enable (bit 0.14) .................................................................................... 64
Data Rate Select (bit 0.13) ..................................................................................... 64
Auto-Negotiation Enable (bit 0.12) ......................................................................... 64
Low Power Mode (bit 0.11) .................................................................................... 65
Isolate (bit 0.10) ..................................................................................................... 65
Restart Auto-Negotiation (bit 0.9) .......................................................................... 65
Duplex Mode (bit 0.8) ............................................................................................. 66
Collision Test (bit 0.7) ............................................................................................ 66
IEEE Reserved Bits (bits 0.6:0) ............................................................................. 66
Register 1: Status Register .................................................................................... 67
100Base-T4 (bit 1.15) ............................................................................................ 67
100Base-TX Full Duplex (bit 1.14) ......................................................................... 68
100Base-TX Half Duplex (bit 1.13) ........................................................................ 68
10Base-T Full Duplex (bit 1.12) ............................................................................. 68
10Base-T Half Duplex (bit 1.11) ............................................................................. 68
IEEE Reserved Bits (bits 1.10:7) ........................................................................... 69
MF Preamble Suppression (bit 1.6) ....................................................................... 69
Auto-Negotiation Complete (bit 1.5) ....................................................................... 69
Remote Fault (bit 1.4) ............................................................................................ 70
Auto-Negotiation Ability (bit 1.3) ............................................................................ 70
Link Status (bit 1.2) ................................................................................................ 71
Jabber Detect (bit 1.1) ........................................................................................... 71
Extended Capability (bit 1.0) .................................................................................. 71
Register 2: PHY Identifier Register ........................................................................ 72
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
Table of Contents
Title
4
Table of Contents
June, 2000
Page