STM32W108CBU64TR STMicroelectronics, STM32W108CBU64TR Datasheet - Page 44

• Manufacturer Part Number: STM32W108CBU64TR
• Description: MCU, RF, 32BIT, 128K FLASH, 48VFQFPN
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU64TR

• Controller Family/series: STM32
• Core Size: 32bit
• No. Of I/o's: 24
• Program Memory Size: 128KB
• Ram Memory Size: 8KB
• Cpu Speed: 24MHz
• Oscillator Type: Internal, External
• No. Of Timers: 2
• Rohs Compliant: Yes
• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System modules
44/209
31
15
31
Reserved
30
14
30
r
Bits [7:4] SLEEPTMR_CLKDIV: Sleep timer prescaler setting
Bit 12 SLEEPTMR_REVERSE:
Bit 11 SLEEPTMR_ENABLE:
Bit 10 SLEEPTMR_DBGPAUSE: Debug Pause
Watchdog restart register (WDOG_RESTART)
Write any value to this register to kick-start the watchdog.
Address:
Reset value:
Sleep timer configuration register (SLEEPTMR_CFG)
This register sets the various options for the Sleep timer.
Address:
Reset value:
Sleep timer count high register (SLEEPTMR_CNTH)
Address:
Reset value:
Bit 0 SLEEPTMR_CLKSEL: Clock Select
29
13
29
SLEEP
TMR_
REVER
SE
0: count forward; 1: count backwards.
Only changes when ENABLE bit is set to ‘0’.
0: disable sleep timer; 1: enable sleep timer.
To change other register bits (REVERSE, CLK_DIV, CLK_SEL), this bit must be set to ‘0’.
Enabling/Disabling latency can be up 2 to 3 clock-periods of selected clock.
0: The timer continues working in Debug mode.
1: The timer is paused in Debug mode when the CPU is halted.
Divides clock by 2
Can only be changed when the ENABLE bit is set to ‘0’.
0: Calibrated 1kHz RC clock (default); 1: 32kHz
Can only be changed when the ENABLE bit is set to ‘0’.
28
28
12
rw
SLEEP
ENABL
TMR_
27
27
11
rw
E
0x4000 6008
0x0000 0000
0x4000 600C
0x0000 0400
0x4000 6010
0x0000 0000
DBGPA
SLEEP
26
TMR_
USE
26
10
rw
N
where N = 0 to 15.
25
25
9
Doc ID 16252 Rev 8
Reserved
r
24
Reserved
24
8
Reserved
23
23
7
SLEEPTMR_CLKDIV
22
22
6
rw
21
21
5
STM32W108CB, STM32W108HB
20
20
4
19
19
3
Reserved
18
18
2
r
17
17
1
16
SLEEP
CLKSE
TMR_
16
rw
0
L