STM32W108CBU64TR STMicroelectronics, STM32W108CBU64TR Datasheet - Page 76

• Manufacturer Part Number: STM32W108CBU64TR
• Description: MCU, RF, 32BIT, 128K FLASH, 48VFQFPN
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU64TR

• Controller Family/series: STM32
• Core Size: 32bit
• No. Of I/o's: 24
• Program Memory Size: 128KB
• Ram Memory Size: 8KB
• Cpu Speed: 24MHz
• Oscillator Type: Internal, External
• No. Of Timers: 2
• Rohs Compliant: Yes
• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial interfaces
Table 14.
1. The notation xxx means that the corresponding column header below is inserted to form the field name.
9.3.2
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MST
1
1
1
SCx_SPICFG
SC_SPIxxx
ORD
0
0
1
SPI master mode formats (continued)
Operation
Characters transmitted and received by the SPI master controller are buffered in transmit
and receive FIFOs that are both 4 entries deep. When software writes a character to the
SCx_DATA register, the character is pushed onto the transmit FIFO. Similarly, when
software reads from the SCx_DATA register, the character returned is pulled from the
receive FIFO. If the transmit and receive DMA channels are used, they also write to and
read from the transmit and receive FIFOs.
When the transmit FIFO and the serializer are both empty, writing a character to the transmit
FIFO clears the SC_SPITXIDLE bit in the SCx_SPISTAT register. This indicates that some
characters have not yet been transmitted. If characters are written to the transmit FIFO until
it is full, the SC_SPITXFREE bit in the SCx_SPISTAT register is cleared. Shifting out a
character to the MOSI pin sets the SC_SPITXFREE bit in the SCx_SPISTAT register. When
the transmit FIFO empties and the last character has been shifted out, the SC_SPITXIDLE
bit in the SCx_SPISTAT register is set.
Characters received are stored in the receive FIFO. Receiving characters sets the
SC_SPIRXVAL bit in the SCx_SPISTAT register, indicating that characters can be read from
the receive FIFO. Characters received while the receive FIFO is full are dropped, and the
SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware
generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error
condition until the receive FIFO is drained. Once the DMA marks a receive error, two
conditions will clear the error indication: setting the appropriate SC_TX/RXDMARST bit in
the SCx_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded.
To receive a character, you must transmit a character. If a long stream of receive characters
is expected, a long sequence of dummy transmit characters must be generated. To avoid
software or transmit DMA initiating these transfers and consuming unnecessary bandwidth,
the SPI serializer can be instructed to retransmit the last transmitted character or to transmit
a busy token (0xFF), which is determined by the SC_SPIRPT bit in the SCx_SPICFG
register. This functionality can only be enabled or disabled when the transmit FIFO is empty
and the transmit serializer is idle, indicated by a cleared SC_SPITXIDLE bit in the
SCx_SPISTAT register.
PHA
1
1
-
(1)
POL
0
1
-
Same as above except data is sent LSB first instead of MSB first.
SCLK
MOSI
SCLK
MOSI
MISO
MISO
out
out
out
out
in
in
Doc ID 16252 Rev 8
TX[7]
RX[7]
RX[7]
TX[7]
RX[6]
TX[6]
TX[6]
RX[6]
RX[5]
RX[5]
TX[5]
TX[5]
Frame formats
TX[4]
RX[4]
RX[4]
TX[4]
TX[3]
RX[3]
TX[3]
RX[3]
STM32W108CB, STM32W108HB
RX[2]
RX[2]
TX[2]
TX[2]
TX[1]
RX[1]
RX[1]
TX[1]
TX[0]
RX[0]
TX[0]
RX[0]