WM8311GEB/V Wolfson Microelectronics, WM8311GEB/V Datasheet - Page 163

• Manufacturer Part Number: WM8311GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 121BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8311GEB/V

• Supply Voltage: 5.5V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 7
• Digital Ic Case Style: BGA
• No. Of Pins: 121
• No. Of Regulated Outputs: 9
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pre-Production
24.4 SUPPLY VOLTAGE MONITORING
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The WM8311 includes a number of mechanisms to prevent the system from starting up, or to force it
to shut down, when the power sources are critically low.
The power supply configuration for the WM8311 is described in Section 17. The chip automatically
chooses the most suitable supply, selecting between a Wall adapter supply, USB or Battery. The
preferred source is routed to the SYSVDD pin, to which the other power management circuits would
typically be connected. The SYSVDD voltage is monitored internally, as described below.
The internal regulator LDO12 is powered from an internal domain equivalent to SYSVDD and
generates an internal supply (VPMIC) to support various “always-on” functions. In the absence of the
Wall, USB or Battery supplies, LDO12 can be powered from a backup battery. (Note that SYSVDD is
not maintained by the backup battery.) The VPMIC monitoring function controls the Power-On Reset
circuit, which sets the threshold below which the WM8311 cannot operate.
The operation of the VPMIC monitoring circuit is illustrated in Figure 38. The internal signal
PORRST
NO POWER state. The internal signal PMICRST
determine when the WM8311 is kept in the BACKUP state.
The VPMIC monitoring thresholds illustrated in Figure 38 are fixed. The voltage levels are defined in
the Electrical Characteristics - see Section 7.5.
Figure 38 VPMIC Monitoring
The operation of the SYSVDD monitoring circuit is illustrated in Figure 39. The V
is the voltage below which the WM8311 forces an OFF transition. This threshold voltage is fixed and
is defined in the Electrical Characteristics - see Section 7.5.
The V
be inhibited if SYSOK is not set. The V
field in accordance with the minimum voltage requirements of the application.
The V
SYSVDD undervoltage condition, at which a selectable response can be initiated. The V
threshold can be set using the SYSLO_THR register field. The action taken under this undervoltage
condition is selected using the SYSLO_ERR_ACT register field, as defined in Table 109. An Interrupt
event is associated with the SYSLO
The SYSLO status can be read from the SYSLO_STS register bit. This bit is asserted when
SYSVDD is below the SYSLO threshold.
¯ ¯ ¯ ¯ ¯ ¯ ¯ is governed by the V
V
V
POR, DE-ASSERT
RES, DE-ASSERT
V
V
PMICRST
POR, ASSERT
Operating
RES, ASSERT
PORRST
SYSOK
SYSLO
V
VPMIC
State
threshold is the level at which the internal signal SYSOK is asserted. Any ON request will
threshold is the level at which the internal signal SYSLO
¯ ¯ ¯ ¯ ¯ ¯ condition - see Section 17.5.
POR
thresholds. These determine when the WM8311 is kept in the
SYSOK
¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ is governed by the V
threshold can be set using the SYSOK_THR register
time
time
time
¯ ¯ ¯ ¯ ¯ ¯ is asserted. This indicates a
PP, December 2009, Rev 3.0
RES
SHUTDOWN
thresholds. These
WM8311
threshold
SYSLO
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