PSB21383H-V13TR Infineon Technologies, PSB21383H-V13TR Datasheet - Page 198
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PSB21383H-V13TR
Manufacturer Part Number
PSB21383H-V13TR
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21383H-V13TR.pdf
(270 pages)
Specifications of PSB21383H-V13TR
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Data Sheet
7.1.9
Value after reset: 00
TIMR
CNT
CNT together with VALUE determine the time period T2 after which a TIN interrupt will
be generated in the normal case:
The timer can be started by setting the STI-bit in CMDR and will be stopped when a TIN
interrupt is generated or the TIMR register is written.
Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration of
VALUE
T1 = ( VALUE + 1 ) x 0.064 sec
7.1.10
Value after reset: FC
SAP1
SAPI1
Value of the first programmable Service Access Point Identifier (SAPI) according to the
ISDN LAPD protocol.
MHA
0: The SAPI address of an incoming frame is compared with SAP1, SAP2, SAPG
1: The SAPI address of an incoming frame is compared with SAP1 and SAPG.
SAP1 can be masked with SAP2 thereby bit positions of SAP1 are not compared
if they are set to ’1’ in SAP2.
T1.
TIMR - Timer Register
SAP1 - SAPI1 Register
7
7
...
... SAPI1 value
... Mask High Address
T = CNT x 2.048 sec + T1 with T1 = ( VALUE+1 ) x 0.064 sec
... Determines the time period T1
CNT
H
H
5
SAPI1
4
188
VALUE
Detailed Register Description
0
0
0
MHA
PSB 21381/2
PSB 21383/4
RD/WR (24
2001-03-12
WR (25
H
H
)
)
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