PSB21383H-V13TR Infineon Technologies, PSB21383H-V13TR Datasheet - Page 231

• Manufacturer Part Number: PSB21383H-V13TR
• Manufacturer: Infineon Technologies

Specifications of PSB21383H-V13TR

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.3.18
Value after reset: 00
MOCR
MRE
0: MONITOR interrupt status MDR generation is masked
1: MONITOR interrupt status MDR generation is enabled
MRC
Determines the value of the MR bit:
0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of
1: MR is internally controlled according to the MONITOR channel protocol. In addition,
MIE
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0).
MXC
Determines the value of the MX bit:
0: The MX bit is always ’1’.
1: The MX bit is internally controlled according to the MONITOR channel
Data Sheet
a packet (if MRE = 1).
the MDR interrupt is enabled for all received bytes according to the MONITOR
channel protocol (if MRE = 1).
protocol.
MOCR - MONITOR Control Register
7
MRE
... MONITOR Receive Interrupt Enable
... MR Bit Control:
... MONITOR Interrupt Enable
... MX Bit Control
MRC
H
MIE
MXC
221
0
0
Detailed Register Description
0
0
0
PSB 21381/2
PSB 21383/4
RD/WR (5E
2001-03-12
H
)