LPC2194HBD64/01-S NXP Semiconductors, LPC2194HBD64/01-S Datasheet - Page 19

• Manufacturer Part Number: LPC2194HBD64/01-S
• Description: MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC 256KB Flash 1.8V/3.3V 64-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of LPC2194HBD64/01-S

• Package: 64LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 60 MHz
• Ram Size: 16 KB
• Program Memory Size: 256 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 16|32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 46
• Interface Type: CAN/I2C/SPI/SSP/UART
• On-chip Adc: 4-chx10-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 2

NXP Semiconductors
LPC2194_5
Product data sheet
6.17.1 Features
6.18.1 Crystal oscillator
6.18.2 PLL
6.18 System control
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output
frequency is called f
purposes of rate equations, etc. f
running and connected. Refer to
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
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Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
osc
Rev. 05 — 10 December 2007
and the ARM processor clock frequency is referred to as CCLK for
Section 6.18.2 “PLL”
osc
and CCLK are the same value unless the PLL is
Single-chip 16/32-bit microcontroller
for additional information.
LPC2194
© NXP B.V. 2007. All rights reserved.
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