LPC2194HBD64/01-S NXP Semiconductors, LPC2194HBD64/01-S Datasheet - Page 21

• Manufacturer Part Number: LPC2194HBD64/01-S
• Description: MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC 256KB Flash 1.8V/3.3V 64-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of LPC2194HBD64/01-S

• Package: 64LQFP
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 60 MHz
• Ram Size: 16 KB
• Program Memory Size: 256 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 16|32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 46
• Interface Type: CAN/I2C/SPI/SSP/UART
• On-chip Adc: 4-chx10-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 2

NXP Semiconductors
LPC2194_5
Product data sheet
CAUTION
6.18.5 External interrupt inputs
6.18.6 Memory mapping control
6.18.7 Power control
6.18.8 APB
Remark: Devices without the /00 or /01 suffixes have only a security level equivalent to
CRP2 available.
The LPC2194 include up to nine edge or level sensitive External Interrupt Inputs as
selectable pin functions. When the pins are combined, external events can be processed
as four independent interrupt signals. The External Interrupt Inputs can optionally be used
to wake-up the processor from Power-down mode.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip SRAM. This allows code running in different memory
spaces to have control of the interrupts.
The LPC2194 support two reduced power modes: Idle mode and Power-down mode. In
Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB so that they can operate at the
speed chosen for the ARM processor. In order to achieve this, the APB may be slowed
down to
power-up (and its timing cannot be altered if it does not work since the APB divider control
registers reside on the APB), the default condition at reset is for the APB to run at
processor clock rate. The second purpose of the APB divider is to allow power savings
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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of the processor clock rate. Because the APB must work properly at
Rev. 05 — 10 December 2007
Single-chip 16/32-bit microcontroller
LPC2194
© NXP B.V. 2007. All rights reserved.
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