LFE2M70E-6FN900C Lattice, LFE2M70E-6FN900C Datasheet - Page 385

IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-900

LFE2M70E-6FN900C

Manufacturer Part Number
LFE2M70E-6FN900C
Description
IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-900
Manufacturer
Lattice
Series
LatticeECP2Mr
Datasheet

Specifications of LFE2M70E-6FN900C

No. Of Logic Blocks
67000
No. Of Macrocells
34000
No. Of Speed Grades
6
Total Ram Bits
4534Kbit
No. Of I/o's
416
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFE2M70E-6FN900C
Manufacturer:
LATTICE
Quantity:
47
Part Number:
LFE2M70E-6FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
September 2007
February 2008
August 2007
June 2008
April 2008
(cont.)
Date
Version
(cont.)
02.8
02.9
03.0
03.1
03.2
Ordering Information
Pinout Information
Pinout Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
Characteristics
Architecture
Architecture
Introduction
Section
(cont.)
sysCLOCK GPLL timing has been updated.
Added ECP2M50 (484/672/900-fpBGA), ECP2M70 (900-fpBGA) and
ECP2M100 (900-fpBGA) pinout information.
1156-fpBGA package option has been removed from the LatticeECP2M
family.
Added Thermal Management text section.
Added LVCMOS33D description.
LatticeECP2M Supply Current has been updated.
Typical Building Block Function Performance, External Switching
Characteristics, Internal Switching Characteristics, Family Timing
Adders, sysCLOCK GPLL Timing, sysCLOCK SPLL Timing, DLL Tim-
ing and sysCONFIG Port Timing Specifications have been updated (tim-
ing rev. A 0.11).
Figure 3-9. Read/Write Mode (Normal) and Figure 3-10. Read/Write
Mode with Input and Output Registers have been updated.
Table 3-8. Channel output Jitter (Max) has been updated.
Signal description has been updated.
Added 1152-fpBGA pinouts for the ECP2M70 and ECP2M100.
Available DDR Interfaces per I/O Bank for the LFE2M35 (484/672-
fpBGA) have been updated.
Family Selection Guide table - Updated number of EBR SRAM Blocks
for the ECP2-70 device.
Removed Read-Before-Write sysMEM EBR mode.
Clarification of the operation of the secondary clock regions.
Removed Read-Before-Write sysMEM EBR mode.
7-3
LatticeECP2/M Family Data Sheet
Change Summary
Revision History

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