MT29F1G08ABBDAH4-IT:D Micron Technology Inc, MT29F1G08ABBDAH4-IT:D Datasheet - Page 18

• Manufacturer Part Number: MT29F1G08ABBDAH4-IT:D
• Manufacturer: Micron Technology Inc

Specifications of MT29F1G08ABBDAH4-IT:D

• Cell Type: NAND
• Density: 8Gb
• Interface Type: Parallel
• Address Bus: 27b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Asynchronous Interface Bus Operation
Table 4: Asynchronous Interface Mode Selection
Asynchronous Enable/Standby
Asynchronous Commands
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
Mode
Standby
Command input
Address input
Data input
Data output
Write protect
1
2
Notes:
The bus on the device is multiplexed. Data I/O, addresses, and commands all share the
same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and com-
mands are always supplied on I/O[7:0].
The command sequence typically consists of a COMMAND LATCH cycle, address input
cycles, and one or more data cycles, either READ or WRITE.
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power con-
sumption.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-
chronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
An asynchronous command is written from I/O[7:0] to the command register on the
rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h), are accepted by die (LUNs) even when they
are busy.
For devices with a x16 interface, I/O[15:8] must be written with zeros when a command
is issued.
1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V
2. WP# should be biased to CMOS LOW or HIGH for standby.
CE#
H
or V
X
L
L
L
L
IL
.
CLE
X
H
X
L
L
L
ALE
18
X
H
X
L
L
L
Asynchronous Interface Bus Operation
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
WE#
H
X
X
RE#
H
H
H
X
X
© 2010 Micron Technology, Inc. All rights reserved.
I/Ox
X
X
X
X
X
X
0V/V
WP#
H
H
H
X
L
CC
IH