MT29F1G08ABBDAH4-IT:D Micron Technology Inc, MT29F1G08ABBDAH4-IT:D Datasheet - Page 47
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MT29F1G08ABBDAH4-IT:D
Manufacturer Part Number
MT29F1G08ABBDAH4-IT:D
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT29F1G08ABBDAH4-ITD.pdf
(93 pages)
Specifications of MT29F1G08ABBDAH4-IT:D
Cell Type
NAND
Density
8Gb
Interface Type
Parallel
Address Bus
27b
Operating Supply Voltage (typ)
1.8V
Operating Temp Range
-40C to 85C
Package Type
VFBGA
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.7V
Operating Supply Voltage (max)
1.95V
Word Size
8b
Number Of Words
128M
Supply Current
20mA
Mounting
Surface Mount
Pin Count
63
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT29F1G08ABBDAH4-IT:D
Manufacturer:
MICRON
Quantity:
1 000
Company:
Part Number:
MT29F1G08ABBDAH4-IT:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT29F1G08ABBDAH4-IT:D
Manufacturer:
MIC
Quantity:
20 000
Column Address Operations
RANDOM DATA READ (05h-E0h)
Figure 31: RANDOM DATA READ (05h-E0h) Operation
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
Cycle type
I/O[7:0]
SR[6]
D
Dn
OUT
Dn + 1
D
The column address operations affect how data is input to and output from the cache
registers within the selected die (LUNs). These features provide host flexibility for man-
aging data, especially when the host internal buffer is smaller than the number of data
bytes or words in the cache register.
When the asynchronous interface is active, column address operations can address any
byte in the selected cache register.
The RANDOM DATA READ (05h-E0h) command changes the column address of the se-
lected cache register and enables data output from the last selected die (LUN). This
command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It
is also accepted by the selected die (LUN) during CACHE READ operations
(RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles contain-
ing the column address, followed by the E0h command, puts the selected die (LUN)
into data output mode. After the E0h command cycle is issued, the host must wait at
least
mode until another valid command is issued.
OUT
t
WHR before requesting data output. The selected die (LUN) stays in data output
t
RHW
Command
05h
Address
C1
47
Address
C2
Command
Micron Technology, Inc. reserves the right to change products or specifications without notice.
E0h
1Gb x8, x16: NAND Flash Memory
t
Column Address Operations
WHR
D
Dk
© 2010 Micron Technology, Inc. All rights reserved.
OUT
Dk + 1
D
OUT
Dk + 2
D
OUT