PSMN3R2-25YLC,115 NXP Semiconductors, PSMN3R2-25YLC,115 Datasheet

MOSFET Power N-Ch 25V 3.4 mOhms

PSMN3R2-25YLC,115

Manufacturer Part Number
PSMN3R2-25YLC,115
Description
MOSFET Power N-Ch 25V 3.4 mOhms
Manufacturer
NXP Semiconductors
Series
-r
Datasheet

Specifications of PSMN3R2-25YLC,115

Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
3.4 mOhms
Drain-source Breakdown Voltage
25 V
Gate-source Breakdown Voltage
20 V
Continuous Drain Current
100 A
Power Dissipation
79 W
Maximum Operating Temperature
+ 175 C
Mounting Style
SMD/SMT
Package / Case
LFPAK
Gate Charge Qg
30 nC
Minimum Operating Temperature
- 55 C
Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
3.4 mOhm @ 25A, 10V
Drain To Source Voltage (vdss)
25V
Current - Continuous Drain (id) @ 25° C
100A
Vgs(th) (max) @ Id
1.95V @ 1mA
Gate Charge (qg) @ Vgs
30nC @ 10V
Input Capacitance (ciss) @ Vds
1781pF @ 12V
Power - Max
79W
Mounting Type
Surface Mount
Lead Free Status / Rohs Status
 Details
Other names
934065203115
1. Product profile
Table 1.
Symbol
V
I
P
T
Static characteristics
R
Dynamic characteristics
Q
Q
D
j
DS
tot
DSon
GD
G(tot)
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
drain-source on-state
resistance
gate-drain charge
total gate charge
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
PSMN3R2-25YLC
N-channel 25 V 3.4 mΩ logic level MOSFET in LFPAK using
NextPower technology
Rev. 01 — 2 May 2011
High reliability Power SO8 package,
qualified to 175°C
Low parasitic inductance and
resistance
DC-to-DC converters
Load switching
Power OR-ing
Conditions
25 °C ≤ T
T
T
V
see
V
see
V
see
mb
mb
GS
GS
GS
Figure 12
Figure 12
Figure
= 25 °C; V
= 25 °C; see
= 4.5 V; I
= 10 V; I
= 4.5 V; I
j
≤ 175 °C
14; see
D
D
D
GS
= 25 A; T
= 25 A; T
= 25 A; V
Figure 2
= 10 V; see
Figure 15
j
j
DS
= 25 °C;
= 25 °C;
= 12 V;
Figure 1
Optimised for 4.5V Gate drive utilising
NextPower Superjunction technology
Ultra low QG, QGD and QOSS for high
system efficiencies at low and high
loads
Server power supplies
Sync rectifier
[1]
Min
-
-
-
-55
-
-
-
-
Product data sheet
Typ
-
-
-
-
3.7
2.85
4
14
-
Max
25
100
79
175
4.45
3.4
-
Unit
V
A
W
°C
mΩ
mΩ
nC
nC

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PSMN3R2-25YLC,115 Summary of contents

Page 1

... PSMN3R2-25YLC N-channel 25 V 3.4 mΩ logic level MOSFET in LFPAK using NextPower technology Rev. 01 — 2 May 2011 1. Product profile 1.1 General description Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment ...

Page 2

... N-channel 25 V 3.4 mΩ logic level MOSFET in LFPAK using NextPower Simplified outline SOT669 (LFPAK; Power-SO8) Description plastic single-ended surface-mounted package; 4 leads Marking code 3C225L All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC Graphic symbol mb G mbb076 [1] © NXP B.V. 2011. All rights reserved Version ...

Page 3

... Figure 3 003aaf840 120 P der (%) 150 200 T (°C) mb Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC Min - = 20 kΩ -20 [1] Figure 1 - Figure ° -55 -55 - 340 - = 25 ° 100 A ...

Page 4

... Product data sheet N-channel 25 V 3.4 mΩ logic level MOSFET in LFPAK using NextPower ( (1) ( DSon All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC 003a a f 854 ( =10 μ 100 μ 100 (V) DS © NXP B.V. 2011. All rights reserved. 003aaf841 ...

Page 5

... Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN3R2-25YLC Product data sheet N-channel 25 V 3.4 mΩ logic level MOSFET in LFPAK using NextPower Conditions see Figure All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC Min Typ Max - 1.72 1.9 003aaf842 t p δ ...

Page 6

... D DS see Figure 14; see Figure MHz °C; see Figure 0.5 Ω 4.7 Ω R G(ext) All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC Min Typ = 25 ° -55 °C 22 °C; 1.05 1.54 = 150 °C 0 -55 ° ° 150 °C ...

Page 7

... 2.8 4 2.6 2.4 2 2 (V) DS Fig 7. Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC Min Typ - 9 003a a f 844 © NXP B.V. 2011. All rights reserved. ...

Page 8

... I (A) D Fig 9. 003a a f 848 V Max (V) GS Fig 11. Gate-source threshold voltage as a function of All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC 100 150 ° Transfer characteristics; drain current as a function of gate-source voltage; typical values ...

Page 9

... 100 I (A) D Fig 13. Normalized drain-source on-state resistance Q GD 003aaa508 Fig 15. Gate-source voltage as a function of gate All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC =10V GS 1.5 1 0 factor as a function of junction temperature ( 20V ...

Page 10

... I ( (V) DS Fig 17. Source current as a function of source-drain All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC 100 150 ° 0.3 0.6 0.9 voltage; typical values 003a a f 444 003a a f 853 = 25 °C ...

Page 11

... D max 4.41 2.2 0.9 0.25 0.30 4.10 4.20 3.62 2.0 0.7 0.19 0.24 3.80 REFERENCES JEDEC JEITA MO-235 All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC detail (1) (1) ( 5.0 3.3 6.2 0.85 1.3 1.27 4.8 3.1 5 ...

Page 12

... NXP Semiconductors 9. Revision history Table 8. Revision history Document ID Release date PSMN3R2-25YLC v.1 20110502 PSMN3R2-25YLC Product data sheet N-channel 25 V 3.4 mΩ logic level MOSFET in LFPAK using NextPower Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. ...

Page 13

... Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC © NXP B.V. 2011. All rights reserved ...

Page 14

... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 May 2011 PSMN3R2-25YLC © NXP B.V. 2011. All rights reserved ...

Page 15

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PSMN3R2-25YLC All rights reserved. Date of release: 2 May 2011 Document identifier: PSMN3R2-25YLC ...

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