LPC1833FET256,551 NXP Semiconductors, LPC1833FET256,551 Datasheet - Page 11

• Manufacturer Part Number: LPC1833FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1833FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293791551

NXP Semiconductors
Table 3.
LPC1850_30_20_10
Objective data sheet
Symbol
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Pin description
F13
G11
F11
B14
A15
C12
B13
C11
…continued
Reset
state
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
Type Description
I/O
O
I/O
O
I/O
I/O
I
O
I/O
I/O
O
O
-
-
I/O
O
I/O
-
-
I/O
I/O
-
-
I/O
I/O
-
I/O
I/O
-
-
I/O
I/O
All information provided in this document is subject to legal disclaimers.
I2S_RX_SCK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I
I2S_RX_MCLK — I2S receive master clock.
I2S_TX_SCK — I
the slave. Corresponds to the signal SCK in the I
I2S_TX_MCLK — I2S transmit master clock.
I2S_TX_WS — Transmit Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I
I2S_RX_WS — Receive Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I
CAN1_RD — CAN1 receiver input.
USB1_IND1 — USB1 port indicator LED control output 1.
I2S_TX_SDA — I
the receiver. Corresponds to the signal SD in the I
I2S_RX_SDA — I
the receiver. Corresponds to the signal SD in the I
CAN1_TD — CAN1 transmitter output.
USB1_IND0 — USB1 port indicator LED control output 0.
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SSP0_SCK — Serial clock for SSP0.
SPIFI_SCK — Serial clock for SPIFI.
GPIO1[14] — General purpose digital input/output pin.
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SPIFI_SIO3 — I/O lane 3 for SPIFI.
GPIO1[15] — General purpose digital input/output pin.
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SPIFI_SIO2 — I/O lane 2 for SPIFI.
GPIO0[6] — General purpose digital input/output pin.
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SSP0_SSEL — Slave Select for SSP0.
SPIFI_MISO — Input I1 in SPIFI quad mode; SPIFI output IO1.
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SSP0_MISO — Master In Slave Out for SSP0.
SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.
Rev. 1.2 — 17 February 2011
2
2
2
S transmit clock. It is driven by the master and received by
S transmit data. It is driven by the transmitter and read by
S Receive data. It is driven by the transmitter and read by
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2
S-bus specification.
2
S-bus specification.
2
2
2
2
S-bus specification.
S-bus specification.
S-bus specification.
S-bus specification.
© NXP B.V. 2011. All rights reserved.
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