LPC1833FET256,551 NXP Semiconductors, LPC1833FET256,551 Datasheet - Page 40

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LPC1833FET256,551

Manufacturer Part Number
LPC1833FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr

Specifications of LPC1833FET256,551

Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
 Details
Other names
935293791551
NXP Semiconductors
LPC1850_30_20_10
Objective data sheet
7.12.3.1 Features
7.12.5.1 Features
7.12.4 SD/MMC card interface
7.12.5 External Memory Controller (EMC)
commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices and includes extensions to help insure compatibility with future
devices.
The SD/MMC card interface supports the following modes to control:
The LPC1850/30/20/10 EMC is a Memory Controller peripheral offering support for
asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it
can be used as an interface with off-chip memory-mapped devices and peripherals.
Interfaces to serial flash memory in the main memory map.
Supports classic and 4-bit bidirectional serial protocols.
Half-duplex protocol compatible with various vendors and devices.
Data rates of up to 40 MB per second total.
Supports DMA access.
Secure Digital memory (SD version 3.0)
Secure Digital I/O (SDIO version 2.0)
Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)
Multimedia Cards (MMC version 4.4)
Dynamic memory interface support including single data rate SDRAM.
Asynchronous static memory device support including RAM, ROM, and NOR flash,
with or without asynchronous page mode.
Low transaction latency.
Read and write buffers to reduce latency and to improve performance.
8/16/32 data and 24 address lines wide static memory support. On parts LPC1820/10
only 8/16 data lines are available.
16 bit and 32 bit wide chip select SDRAM memory support.
Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
Four chip selects for synchronous memory and four chip selects for static memory
devices.
Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
Dynamic memory self-refresh mode controlled by software.
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 17 February 2011
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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