LPC1833FET256,551 NXP Semiconductors, LPC1833FET256,551 Datasheet - Page 6

• Manufacturer Part Number: LPC1833FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1833FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293791551

NXP Semiconductors
6. Pinning information
Table 3.
LPC1850_30_20_10
Objective data sheet
Symbol
Multiplexed digital pins
P0_0
P0_1
[2]
[2]
Pin description
6.1 Pinning
6.2 Pin description
L3
M2
On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA
to PF, with up to 20 pins used per port. Each digital pin may support up to four different
digital functions, including General Purpose I/O (GPIO), selectable through the SCU
registers. Note that the pin name is not indicative of the GPIO port assigned to it.
Analog functions and power pins are pinned out separately and do not share pins with
digital functions.
Fig 2.
Reset
state
[1]
I; PU
I; PU
Pin configuration LBGA256 package
Type Description
I/O
I/O
I
-
I/O
I/O
I
-
All information provided in this document is subject to legal disclaimers.
GPIO0[0] — General purpose digital input/output pin.
SSP1_MISO — Master In Slave Out for SSP1.
ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
n.c.
GPIO0[1] — General purpose digital input/output pin.
SSP1_MOSI — Master Out Slave in for SSP1.
ENET_COL — Ethernet Collision detect (MII interface).
n.c.
Rev. 1.2 — 17 February 2011
ball A1
index area
D
H
M
B
F
K
P
T
A
C
E
G
N
R
L
J
1
2
3
4
LPC1850/30FET256
Transparent top view
5
6
7
8
32-bit ARM Cortex-M3 microcontroller
9
10
LPC1850/30/20/10
11
12
13
14
002aaf230
15
16
© NXP B.V. 2011. All rights reserved.
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