ST72C334N2B6 STMicroelectronics, ST72C334N2B6 Datasheet - Page 63

• Manufacturer Part Number: ST72C334N2B6
• Description: Microcontrollers (MCU) Flash 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72C334N2B6

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: SDIP-56
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

16-BIT TIMER (Cont’d)
6.4.3.7 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corre-
2. Load the OC1R register with the value corre-
3. Select the following in the CR1 register:
4. Select the following in the CR2 register:
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OC
ing application can be calculated using the follow-
ing formula:
Where:
t
f
PRESC
CPU
sponding to the period of the signal.
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
– Set OC1E bit: the OCMP1 pin is then dedicat-
– Set the PWM bit.
– Select the timer clock (CC1-CC0) (see Table
plied to the OCMP1 pin after a successful
comparison with OC1R register.
plied to the OCMP1 pin after a successful
comparison with OC2R register.
ed to the output compare 1 function.
14 Clock Control Bits).
i
R register value required for a specific tim-
= Desired output compare period (in sec-
= Internal clock frequency
= Timer prescaler factor (2, 4 or 8 de-
OC i R Value =
onds)
pending on CC1-CC0 bits, see Table 14
Clock Control Bits)
PRESC
t
*
f
CPU
- 5
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 45).
Notes:
1. After a write instruction to the OC i HR register,
2. The OCF1 and OCF2 bits cannot be set by
3. The ICF1 bit is set by hardware when the coun-
4. In PWM mode the ICAP1 pin can not be used
5. When the Pulse Width Modulation (PWM) and
the output compare function is inhibited until the
OC i LR register is also written.
Therefore the Input Capture 1 function is inhib-
ited but the Input Capture 2 is available.
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
ST72334J/N, ST72314J/N, ST72124J
Counter
= OC1R
Counter
= OC2R
When
When
Pulse Width Modulation cycle
OCMP1 = OLVL2
OCMP1 = OLVL1
Counter is reset
ICF1 bit is set
to FFFCh
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