LFEC6E-5FN484C Lattice, LFEC6E-5FN484C Datasheet - Page 113

• Manufacturer Part Number: LFEC6E-5FN484C
• Description: FPGA - Field Programmable Gate Array 6.1 LUT 224 I/O
• Manufacturer: Lattice

Specifications of LFEC6E-5FN484C

• Number Of Gates: 6100
• Number Of Logic Blocks: 768
• Number Of Macrocells: 6100
• Maximum Operating Frequency: 420 MHz
• Number Of Programmable I/os: 224
• Data Ram Size: 94208
• Delay Time: 5 ns
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: FPBGA-484
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / Rohs Status: Details

Lattice Semiconductor
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
Number
Ball
N13
N14
R15
M17
N16
N17
G11
H10
H11
G12
H12
H13
H14
M15
M16
N15
R12
R13
R14
R10
R11
P10
P11
P12
P13
P14
K16
K17
L17
P16
K15
L15
L16
P15
T12
J16
J15
N9
R8
M6
N6
N7
H9
R9
P9
K6
K7
L6
P7
J7
Function
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Ball
LFECP6/LFEC6
Bank LVDS
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Function
Dual
Number
Ball
N13
N14
R15
M17
N16
N17
G11
H10
H11
G12
H12
H13
H14
M15
M16
N15
R12
R13
R14
R10
R11
P10
P11
P12
P13
P14
K16
K17
L17
P16
K15
L15
L16
P15
T12
J16
J15
N9
R8
M6
N6
N7
H9
R9
P9
K6
K7
L6
P7
J7
Function
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Ball
LFECP10/LFEC10
Bank LVDS
4-47
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Function
Dual
LatticeECP/EC Family Data Sheet
Number
M17
M15
M16
Ball
N13
N14
P10
P11
P12
P13
P14
R15
K16
K17
N16
N17
P16
G11
H10
H11
G12
H12
H13
H14
K15
N15
P15
R12
R13
R14
R10
R11
J16
L17
J15
L15
L16
T12
N9
R8
M6
N6
N7
H9
R9
P9
J7
K6
K7
L6
P7
Function
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Ball
LFECP/LFEC15
Pinout Information
Bank LVDS
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Function
Dual