LFEC6E-5FN484C Lattice, LFEC6E-5FN484C Datasheet - Page 6

• Manufacturer Part Number: LFEC6E-5FN484C
• Description: FPGA - Field Programmable Gate Array 6.1 LUT 224 I/O
• Manufacturer: Lattice

Specifications of LFEC6E-5FN484C

• Number Of Gates: 6100
• Number Of Logic Blocks: 768
• Number Of Macrocells: 6100
• Maximum Operating Frequency: 420 MHz
• Number Of Programmable I/os: 224
• Data Ram Size: 94208
• Delay Time: 5 ns
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: FPBGA-484
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / Rohs Status: Details

Lattice Semiconductor
PFU and PFF Blocks
The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
Latch
FF/
LUT4 &
CARRY
D
Slice 0
Latch
FF/
LUT4 &
CARRY
D
Latch
FF/
LUT4 &
CARRY
D
Slice 1
Latch
FF/
LUT4 &
CARRY
D
Routing
Routing
From
2-3
To
Latch
FF/
LUT4 &
CARRY
D
Slice 2
Latch
FF/
LUT4 &
CARRY
LatticeECP/EC Family Data Sheet
D
Latch
FF/
LUT4 &
CARRY
D
Slice 3
Latch
FF/
LUT4 &
CARRY
D
Architecture