LFEC6E-5FN484C Lattice, LFEC6E-5FN484C Datasheet - Page 34
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LFEC6E-5FN484C
Manufacturer Part Number
LFEC6E-5FN484C
Description
FPGA - Field Programmable Gate Array 6.1 LUT 224 I/O
Manufacturer
Lattice
Datasheet
1.LFECP15E-5FN256C.pdf
(163 pages)
Specifications of LFEC6E-5FN484C
Number Of Gates
6100
Number Of Logic Blocks
768
Number Of Macrocells
6100
Maximum Operating Frequency
420 MHz
Number Of Programmable I/os
224
Data Ram Size
94208
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA-484
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC6E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Table 2-14. Supported Output Standards
Hot Socketing
The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and
power-down. Power supplies can be sequenced in any order. During power up and power-down sequences, the
I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition,
leakage into I/O pins is controlled within specified limits, this allows for easy integration with the rest of the sys-
tem. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applica-
tions.
Configuration and Testing
The following section describes the configuration and testing features of the LatticeECP/EC devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test
access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
Single-ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
HSTL18 Class I, II, III
HSTL15 Class I, III
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I
Differential HSTL18, Class I, II, III
Differential HSTL15, Class I, III
LVDS
BLVDS
LVPECL
RSDS
1. Emulated with external resistors.
1
1
1
Output Standard
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA, 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
2-31
4mA, 8mA, 12mA, 16mA
4mA, 8mA, 12mA 16mA
4mA, 8mA
2mA, 6mA
4mA, 8mA
2mA, 6mA
Drive
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LatticeECP/EC Family Data Sheet
V
CCIO
3.3
3.3
2.5
1.8
1.5
1.2
3.3
1.8
1.5
3.3
2.5
3.3
2.5
1.8
1.8
1.5
2.5
2.5
3.3
2.5
—
—
—
1.8
—
—
(Nom.)
Architecture
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