LFEC6E-5FN484C Lattice, LFEC6E-5FN484C Datasheet - Page 27
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LFEC6E-5FN484C
Manufacturer Part Number
LFEC6E-5FN484C
Description
FPGA - Field Programmable Gate Array 6.1 LUT 224 I/O
Manufacturer
Lattice
Datasheet
1.LFECP15E-5FN256C.pdf
(163 pages)
Specifications of LFEC6E-5FN484C
Number Of Gates
6100
Number Of Logic Blocks
768
Number Of Macrocells
6100
Maximum Operating Frequency
420 MHz
Number Of Programmable I/os
224
Data Ram Size
94208
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA-484
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC6E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-27. Input Register DDR Waveforms
Figure 2-28. INDDRXB Primitive
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-29 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
(In DDR Mode)
Delayed
DQS
DQS
D0
D2
DI
DDRCLKPOL
A
ECLK
SCLK
LSR
CE
D
B
2-24
IDDRXB
C
B
A
QA
QB
LatticeECP/EC Family Data Sheet
D
E
D
C
F
Architecture
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