LFE2M50SE-7FN900C Lattice, LFE2M50SE-7FN900C Datasheet - Page 17
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2M50SE-7FN900C
Manufacturer Part Number
LFE2M50SE-7FN900C
Description
FPGA - Field Programmable Gate Array 48K LUTs 410 S Ser Memory DSP 1.2V 7SPD
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2M50SE-7FN900C
Number Of Macrocells
48000
Number Of Programmable I/os
410
Data Ram Size
4246528
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA-900
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50SE-7FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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- Download datasheet (3Mb)
Lattice Semiconductor
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12.
Figure 2-12. Edge Clock Sources
From Routing
From Routing
Sources for left edge clocks
Input
Input
DLL
PLL
Clock
Clock
Input
Input
DLLDELA
GPLL
DLL
Routing
Routing
From
From
Eight Edge Clocks (ECLK)
Two Clocks per Edge
Clock Input
Clock Input
2-14
Clock Input
Clock Input
Routing
Routing
From
From
Sources for top
LatticeECP2/M Family Data Sheet
bottom edge
Sources for
edge clocks
clocks
Sources for right edge clocks
GPLL
DLL
DLLDELA
Architecture
From Routing
From Routing
Clock
Clock
Input
Input
Input
Input
DLL
PLL
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