LFE2M50SE-7FN900C Lattice, LFE2M50SE-7FN900C Datasheet - Page 382

• Manufacturer Part Number: LFE2M50SE-7FN900C
• Description: FPGA - Field Programmable Gate Array 48K LUTs 410 S Ser Memory DSP 1.2V 7SPD
• Manufacturer: Lattice

Specifications of LFE2M50SE-7FN900C

• Number Of Macrocells: 48000
• Number Of Programmable I/os: 410
• Data Ram Size: 4246528
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: FPBGA-900
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / Rohs Status: Details

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© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
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September 2006
For Further Information
A variety of technical notes for the LatticeECP2 family are available on the Lattice web site at www.latticesemi.com.
For further information about interface standards refer to the following web sites:
• LatticeECP2M SERDES/PCS Usage Guide (TN1124)
• LatticeECP2/M sysIO Usage Guide (TN1102)
• LatticeECP2/M sysCLOCK PLL Design and Usage Guide (TN1103)
• LatticeECP2/M Memory Usage Guide (TN1104)
• LatticeECP2/M High-Speed I/O Interface (TN1105)
• Power Estimation and Management for LatticeECP2/M Devices (TN1106)
• LatticeECP2/M sysDSP Usage Guide (TN1107)
• LatticeECP2/M sysCONFIG Usage Guide (TN1108)
• LatticeECP2/M Configuration Encryption Usage Guide (TN1109)
• LatticeECP2/M Soft Error Detection (SED) Usage Guide (TN1113)
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: www.pcisig.com
LatticeECP2/M Family Data Sheet
6-1
Supplemental Information
DS1006
Data Sheet DS1006
Further Info_01.0