LFE2M50SE-7FN900C Lattice, LFE2M50SE-7FN900C Datasheet - Page 219
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2M50SE-7FN900C
Manufacturer Part Number
LFE2M50SE-7FN900C
Description
FPGA - Field Programmable Gate Array 48K LUTs 410 S Ser Memory DSP 1.2V 7SPD
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2M50SE-7FN900C
Number Of Macrocells
48000
Number Of Programmable I/os
410
Data Ram Size
4246528
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA-900
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50SE-7FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)
Lattice Semiconductor
Ball Number
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
W27
W28
W29
W30
V23
V26
V24
U25
U23
V29
V30
U26
U24
U27
U28
U29
U30
R24
R26
R23
R25
R27
R28
P26
P24
R29
R30
T23
T25
T24
T26
T27
T28
T29
T30
Ball/Pad Function
GNDIO3
GNDIO3
GNDIO2
GNDIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO2
PR70A
PR69B
PR69A
PR68B
PR68A
PR67B
PR67A
PR66B
PR66A
PR65B
PR65A
PR64B
PR64A
PR63B
PR63A
PR62B
PR62A
PR61B
PR61A
PR60B
PR60A
PR59B
PR59A
PR57B
PR57A
PR56B
PR56A
PR55B
PR55A
PR54B
PR54A
PR53B
PR53A
PR52B
PR52A
LFE2-70E/SE
Bank
4-119
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
-
-
PCLKC3_0/RDQ63
PCLKC2_0/RDQ54
PCLKT3_0/RDQ63
PCLKT2_0/RDQ54
LatticeECP2/M Family Data Sheet
VREF2_3/RDQ63
VREF1_3/RDQ63
Dual Function
RDQS63
RDQS54
RDQ71
RDQ71
RDQ71
RDQ71
RDQ71
RDQ71
RDQ71
RDQ63
RDQ63
RDQ63
RDQ63
RDQ63
RDQ63
RDQ63
RDQ63
RDQ63
RDQ63
RDQ63
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
RDQ54
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
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