LFE2M50SE-7FN900C Lattice, LFE2M50SE-7FN900C Datasheet - Page 253
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2M50SE-7FN900C
Manufacturer Part Number
LFE2M50SE-7FN900C
Description
FPGA - Field Programmable Gate Array 48K LUTs 410 S Ser Memory DSP 1.2V 7SPD
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2M50SE-7FN900C
Number Of Macrocells
48000
Number Of Programmable I/os
410
Data Ram Size
4246528
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA-900
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50SE-7FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFE2M50E/SE Logic Signal Connections: 484 fpBGA
Ball Number
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
VCCIO
D1
E1
G6
G1
G2
H1
H2
H7
H6
G3
H3
H5
H4
K1
K2
K5
K7
K6
F1
F2
F5
F4
F3
L6
L7
J1
J2
J3
J4
J7
J6
J5
Ball/Pad Function
GNDIO7
GNDIO7
GNDIO7
GNDIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL14B
PL32A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
PL35B
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
PL9B
LFE2M50E/SE
4-153
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
LUM3_SPLLC_FB_A/LDQ36
LUM3_SPLLC_IN_A/LDQ36
LUM3_SPLLT_FB_A/LDQ36
LUM3_SPLLT_IN_A/LDQ36
LatticeECP2/M Family Data Sheet
LUM0_SPLLC_FB_A
LUM0_SPLLT_FB_A
LUM0_SPLLC_IN_A
LUM0_SPLLT_IN_A
VREF2_7/LDQ6
VREF1_7/LDQ6
Dual Function
LDQS6
LDQ36
LDQ36
LDQ36
LDQ36
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
LDQ6
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
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