LFE2M50SE-7FN900C Lattice, LFE2M50SE-7FN900C Datasheet - Page 21

• Manufacturer Part Number: LFE2M50SE-7FN900C
• Description: FPGA - Field Programmable Gate Array 48K LUTs 410 S Ser Memory DSP 1.2V 7SPD
• Manufacturer: Lattice

Specifications of LFE2M50SE-7FN900C

• Number Of Macrocells: 48000
• Number Of Programmable I/os: 410
• Data Ram Size: 4246528
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Package / Case: FPBGA-900
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / Rohs Status: Details

Lattice Semiconductor
Figure 2-19. Edge Clock Mux Connections
sysMEM Memory
LatticeECP2/M devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-
Kbit RAM with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6. FIFOs can be implemented in sysMEM EBR blocks by imple-
menting support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for
each data byte. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths.
GPLL Output CLKOP
GPLL Output CLKOS
DLL Output CLKOP
DLL Output CLKOS
Clock Input Pad
GPLL Input Pad
GPLL Input Pad
Input Pad
Input Pad
Routing
Routing
Routing
CLKO
CLKO
2-18
Top and Bottom
ECLK1/ ECLK2
Left and Right
Left and Right
Edge Clocks
Edge Clocks
Edge Clocks
(Both Mux)
LatticeECP2/M Family Data Sheet
ECLK1
ECLK2
Architecture