SFSA16GBQ1BR8TO-I-DT-216-STD Swissbit NA Inc, SFSA16GBQ1BR8TO-I-DT-216-STD Datasheet - Page 27

• Manufacturer Part Number: SFSA16GBQ1BR8TO-I-DT-216-STD
• Description: FLASH SSD UDMA IND 2.5" 16GB
• Manufacturer: Swissbit NA Inc
• Series: X-200r

Specifications of SFSA16GBQ1BR8TO-I-DT-216-STD

• Memory Size: 16GB
• Memory Type: FLASH - NAND
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1030

6.21 Security Unlock (F2h)
This command requests transfer of a single sector of data from the host. Table 34 defines the content of this
sector of information. If the identifier bit is set to Master and the device is in high security level, then the
password supplied shall be compared with the stored Master password. If the device is in the maximum security
level, then the unlock command shall be rejected. If the identifier bit is set to user, then the device compares
the supplied password with the stored User password. If the password compare fails then the device returns
command aborted to the host and decrements the unlock counter. This counter is initially set to five and is
decremented for each password mismatch when Security Unlock is issued and the device is locked. Once this
counter reaches zero, the Security Unlock and Security Erase Unit commands are command aborted until after a
power-on reset or a hardware reset is received. Security Unlock commands issued when the device is unlocked
have no effect on the unlock counter.
Table 41: Security Unlock
6.22 Set Features (EFh)
This command is used by the host to establish or select certain features. If any subcommand input value is not
supported or is invalid, the SSD returns command aborted.
Table 42: Set Features
Table 43: Features Supported
Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h feature
command is issued all data transfers shall occur on the low order D[7:0] data bus and the -IOIS16 signal shall
not be asserted for data register accesses. The host shall not enable this feature for DMA transfers.
Swissbit AG
Industriestrasse 4-8
CH-9552 Bronschhofen
Switzerland
Task File Register
COMMAND
DRIVE/HEAD
CYLINDER HI
CYLINDER LOW
SECTOR NUM
SECTOR COUNT
FEATURES
Task File Register
COMMAND
DRIVE/HEAD
CYLINDER HI
CYLINDER LOW
SECTOR NUM
SECTOR COUNT
FEATURES
09h/89h
05h/85h
0Ah/8Ah
02h/82h
55h/AAh
66h/CCh
Feature
01h/81h
69h
96h
BBh
03h
9Ah
97h
Operation
Enable/Disable 8-bit data transfers.
Enable/Disable write cache.
Set transfer mode based on value in Sector Count register.
Enable/Disable advance power management.
Enable/Disable extended power operations.
Enable/Disable power level 1 commands.
Disable/Enable Read Look Ahead.
Disable/Enable Power On Reset (POR) established of defaults at Soft Reset.
NOP Accepted for backward compatibility.
NOP Accepted for backward compatibility.
Accepted for backward compatibility. Use of this Feature is not recommended.
Set the host current source capability.
Allows trade-off between current drawn and read/write speed.
4 bytes of data apply on Read/Write Long commands
Swissbit reserves the right to change products or specifications without notice.
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[e-mail]
LBA
www.swissbit.com
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5
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5
D
4
D
4
Feature
Config
F2h
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nu
nu
nu
EFh
nu
nu
nu
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