Z8622912PSG Zilog, Z8622912PSG Datasheet - Page 22

• Manufacturer Part Number: Z8622912PSG
• Description: IC CCD W/2ND I2C ADD 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CGROM
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

SERIAL COMMUNICATIONS INTERFACE
Commands and data are sent to and from the Z86229
through its serial communications interface. Two Serial
Control Modes are available. One mode is a two wire I
bus interface. The other serial mode is a three wire, syn-
chronous serial peripheral interface (SPI). In both cases, the
Z86229 acts as a slave device.
The serial communications port is the path for setting the
configuration and operational modes of the device. It is also
the port for outputting the recovered XDS data and for in-
putting the OSD data for display.
When the Vertical Lock = VIDEO, the V
is configured as an output, providing the INTRO signal.
This interrupt operation is available in either serial control
mode.
The Z86229 is able to generate an interrupt on the occurrence
of any set of specified events. The master device clears the
interrupt by writing to the Interrupt Request Register.
I
The serial control mode in use is selected by the state of the
SMS pin. When SMS is set Low, the Z86229 is in the I
mode. In this mode, the Z86229 also supports a bidirectional
two wire bus and data transmission protocol. The bus is con-
trolled by the master device, which generates the serial
clock (SCK), controls the bus access, and generates the Start
and Stop conditions. The SDA pin is the bidirectional data
line. In this mode, the SDO output is not used, and the pin
is in its high-impedance state.
The Z86229 can receive or transmit data under the control
of a master device. Remember that the Z86229 is a slave
device. Communication is initiated when the master device
sends the start condition followed by the Z86229 Slave Ad-
dress Read byte (29h or 2Bh) or Slave Address Write byte
(28h or 2Ah). The Z86229 responds with an Acknowledge.
The I
the I
Note: *When the SMS and SEN pins are both Low, the part is in
the Reset state. Therefore, the SEN pin can be used to reset the
part while in the I
signal or tied High if no reset is required. The I
selected by pin 1 input. When pin 1 input is Low(0), it selects the
1st address. When pin 1 input is High(1), it selects the second
address.
2
C Bus Operation
2

2
C addresses (Table 10).

C RD/nWR bit is the Least Significant Bit (LSB) of
Table 10. Z8612 I
2
C mode. The SEN pin may be tied to a NReset
2
C Slave Addresses*
IN
/INTRO (pin13)
2
C Address is
2
2
C
C
The I
Under the I
be present:
1. Data transfer can only be started when the bus is not busy.
2. During data transfer, data transitions must not occur
Bus Conditions are Defined as:
Not Busy.
Start.
SCK line is High.
Stop.
SCK line is High.
Acknowledge.
output an acknowledge after the reception of each byte. The
master device must generate the clock for the acknowledge
bit. Acknowledge is SDA=Low. A Not ACKnowledge re-
sult (NACK) is SDA=High.
Data.
on the falling edge of SCK, MSB first. The receiving device
reads the data, MSB first, on the rising edge of SCK.
Communication with the Z86229 is initiated when the mas-
ter device sends the Z86229 slave address following a start
condition. The Z86229 has a single preset, consisting of a
seven-bit slave address. The Z86229 responds with an ac-
knowledge. The eighth bit of the slave address is driven
High for Read operations and Low for Write operations.
Writing to the I
All write commands are either one- or two-byte commands.
The Z86229 is enabled when a Start condition, followed by
its Slave Address Write byte, is received. The Start condi-
tion is disabled when it deems the command to have been
completed, or when a Stop condition occurs. A new Start
condition without a Stop condition begins a new sequence.
Therefore, successive commands may be executed by suc-
cessive strings of “Start
quences without any intervening Stop condition being sent.
Note:
while the clock is High.
A Low to High transition of an SDA line while the
The number of data bytes to be received by the Z86229 is
2
A High to Low transition of an SDA line while the
The data (SDA) is output by the transmitting device
inherent in the command. The Z86229 responds with the
acknowledge signal only for the number of bytes expect-
ed. If the master writes more bytes than expected, there is
no acknowledge for the extra bytes.
C Bus Protocol
Data and Clock lines are both High.
2
C bus protocol, the following conditions must
When addressed, the receiving device must
2
C Bus
—
Slave Address
—
Command” se-
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