DS90CR482VS/NOPB National Semiconductor, DS90CR482VS/NOPB Datasheet - Page 11

• Manufacturer Part Number: DS90CR482VS/NOPB
• Description: IC SERIALIZER 48BIT 100-TQFP
• Manufacturer: National Semiconductor

Specifications of DS90CR482VS/NOPB

• Function: Serializer/Deserializer
• Data Rate: 5.38Gbps
• Input Type: LVDS
• Output Type: CMOS, TTL
• Number Of Inputs: 8
• Number Of Outputs: 48
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS90CR482VS; DS90CR482VS

AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
See Applications Information section for more details.
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
See Applications Informations section for more details.
j
j
j
j
j
j
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
d= Tppos — Transmitter output pulse position (min and max)
f= Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate)
m= extra margin - assigned to ISI in long cable applications
FIGURE 13. Receiver Skew Margin (RSKM) for Chipset without DESKEW
FIGURE 14. Receiver Skew Margin (RSKMD) for Chipset with DESKEW
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