PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet - Page 35

• Manufacturer Part Number: PI7C9X7954AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7954AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.46. EEPROM CONTROL REGISTER – OFFSET DCh
6.2.47. PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h
6.2.48. NEXT ITEM POINTER REGISTER – OFFSET E0h
6.2.49. PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h
September 2009 – Revision 1.3
Pericom Semiconductor
BIT
15:8
23:16
31:24
BIT
0
1
2
4:3
15:5
31:16
BIT
7:0
BIT
15:8
BIT
19:16
23:20
24
29:25
31:30
FUNCTION
GPIO I/O Enable
GPIO Output
Reserved
FUNCTION
Enhanced
Capabilities ID
Next Item Pointer
FUNCTION
EEPROM Start
Reserved
EEPROM Preload
Control
EEPROM
Operation
Command
EEPROM Address
EEPROM Write
DATA Buffer
FUNCTION
FUNCTION
Capability Version
Device/Port Type
Slot Implemented
Interrupt Message
Number
Reserved
09-0088
TYPE
TYPE
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RO
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Starts the EEPROM read or write cycle.
Reset to 0b.
Reset to 0b.
Enable preload start.
Reset to 0b.
EEPROM Operation Command.
00b: Reserved
01b: Write operation command
10b: Read operation command
11b: Reserved
Reset to 00b.
EEPROM RW address.
Reset to 000h.
EEPROM write data buffer register.
Reset to 0000h.
DESCRIPTION
These 8 bits determine whether the GPIO pins are input or output
pins. Bit[x+8] corresponds to GPIO[x], where x=7 to 0. If the bit is
set to “0”, the corresponding GPIO pin is an input pin. If the bit is set
to “1”, the corresponding GPIO pin is an output pin.
The current state of the GPIO[x] pin can be written by bit[x+16] in
this register, where x=7 to 0. The bits are effective only when the
corresponding GPIO I/O Enable bits are set to “1”.
Reserved
DESCRIPTION
Read as 10h to indicate that these are PCI express enhanced
capability registers.
DESCRIPTION
Read as 00h. No other ECP registers.
Reset to 00h.
DESCRIPTION
Read as 0001b to indicate the I/O bridge is compliant to Revision
1.0a of PCI Express Base Specifications.
Indicates the type of Legacy PCI Express Endpoint device.
Reset to 1h.
It is not implemented. Hardwired to 00000b.
Reset to 00b.
It is not implemented. Hardwired to 0b.
PCI Express® Quad UART
PI7C9X7954
Datasheet