PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet - Page 45

• Manufacturer Part Number: PI7C9X7954AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7954AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Each register in the UART Register Block can be access by adding an offset to the UART I/O Base Address.
The following table lists the arrangement of the registers in the UART Register Block in I/O mode.
7.1.1.
7.1.2.
7.1.3.
September 2009 – Revision 1.3
Pericom Semiconductor
RECEIVE HOLDING REGISTER – OFFSET 00h
TRANSMIT HOLDING REGISTER – OFFSET 00h
INTERRUPT ENABLE REGISTER – OFFSET 01h
Table 7-2 Registers in I/O Mode
UART I/O Base Address + 00h
UART I/O Base Address + 00h
UART I/O Base Address + 01h
UART I/O Base Address + 02h
UART I/O Base Address + 02h
UART I/O Base Address + 03h
UART I/O Base Address + 04h
UART I/O Base Address + 05h
UART I/O Base Address + 06h
UART I/O Base Address + 07h
UART I/O Base Address + 00h
UART I/O Base Address + 01h
UART I/O Base Address + 02h
BIT
7:0
BIT
7:0
BIT
0
1
2
3
4
5
FUNCTION
Rx Holding
FUNCTION
Tx Holding
FUNCTION
Rx Data Available
Interrupt
Tx Empty Interrupt
Rx Status Interrupt
Modem Status
Interrupt
Xoff/Special
character interrupt
RTS Interrupt
Offset
09-0088
Additional Standard Registers (Required LCR[7] = 1)
RO
WO
RW
RW
RW
RW
RW
RW
TYPE
TYPE
TYPE
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
Interrupt Status Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Special Function register
Division Latch Low
Division Latch High
Sample Clock Register
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DESCRIPTION
Data received
Reset to 00h.
DESCRIPTION
Data to transmit
Reset to 00h.
DESCRIPTION
0b: Disable the Receive Data Ready Interrupt
1b: Enable the Receive Data Ready Interrupt
Reset to 0b.
0b: Disable the Transmit Holding Register Empty Interrupt
1b: Enable the Transmit Holding Register Empty Interrupt
Reset to 0b.
0b: Disable the Receive Line Status Interrupt
1b: Enable the Receive Line Status Interrupt
Reset to 0b.
0b: Disable the Modem Status Register Interrupt
1b: Enable the Modem Status Register Interrupt
Reset to 0b.
0b: Disable the Software Flow Control Interrupt
1b: Enable the Software Flow Control Interrupt
Reset to 0b.
0b: Disable RTS/DTR Interrupt
1b: Enable RTS/DTR Interrupt
Reset to 0b.
Register Name
Mnemonic
MCR
RHR
MSR
DLH
THR
FCR
LCR
DLL
SCR
LSR
SFR
IER
ISR
PCI Express® Quad UART
Register Type
PI7C9X7954
WO
WO
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
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