PI7C9X7958ANBE Pericom Semiconductor, PI7C9X7958ANBE Datasheet - Page 53

IC PCIE-TO-UART BRIDGE 160LFBGA

PI7C9X7958ANBE

Manufacturer Part Number
PI7C9X7958ANBE
Description
IC PCIE-TO-UART BRIDGE 160LFBGA
Manufacturer
Pericom Semiconductor
Datasheets

Specifications of PI7C9X7958ANBE

Applications
PCIe-to-Uart Bridge
Interface
Advanced Configuration Power Interface (ACPI)
Voltage - Supply
1.8V, 3.3V
Package / Case
160-LFBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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11-0039
7.2.2.
7.2.3.
7.2.4.
March 2011 – Revision 1.4
Pericom Semiconductor
TRANSMIT HOLDING REGISTER – OFFSET 00h
INTERRUPT ENABLE REGISTER – OFFSET 01h
INTERRUPT STATUS REGISTER – OFFSET 02h
BIT
7:0
BIT
7:0
BIT
0
1
2
3
4
5
6
7
BIT
FUNCTION
Rx Holding
FUNCTION
Tx Holding
FUNCTION
Rx Data Available
Interrupt
Tx Empty Interrupt
Rx Error Status
Modem Status
Interrupt
Xoff/Special
character interrupt
RTS Interrupt
CTS Interrupt
Reserved
FUNCTION
RO
WO
RW
RW
RW
RW
RW
RW
RW
RW
TYPE
TYPE
TYPE
TYPE
Page 53 of 71
DESCRIPTION
When data are read from the Receive Holding Register (RHR),
they are removed from the top of the receiver’s associated
FIFOs, which holds a queue of data received by the receiver.
Data read from the RHR when the FIFOs are empty are invalid.
The Line Status Register (LSR) indicates the full or empty status
of the FIFOs.
Reset to 00h.
DESCRIPTION
When data are written to the Transmit Holding Register (THR),
they are written to the bottom of the transmitter’s associated
FIFOs, which holds a queue of data to be transmitted by the
transmitter.
Data written to the THR when the FIFOs are full are lost. The
Line Status Register (LSR) indicates the full or empty status of
the FIFOs.
Reset to 00h.
DESCRIPTION
0b: Disable the Receive Data Ready Interrupt
1b: Enable the Receive Data Ready Interrupt
Reset to 0b.
0b: Disable the Transmit Holding Register Empty Interrupt
1b: Enable the Transmit Holding Register Empty Interrupt
Reset to 0b.
0b: Disable the Receive Line Status Interrupt
1b: Enable the Receive Line Status Interrupt
Reset to 0b.
0b: Disable the Modem Status Register Interrupt
1b: Enable the Modem Status Register Interrupt
Reset to 0b.
0b: Disable the Software Flow Control Interrupt
1b: Enable the Software Flow Control Interrupt
Reset to 0b.
0b: Disable RTS/DTR Interrupt
1b: Enable RTS/DTR Interrupt
Reset to 0b.
0b: Disable CTS/DSR interrupt
1b: Enable CTS/DSR interrupt
Reset to 0b.
Reset to 0b.
DESCRIPTION
PCI Express® Octal UART
PI7C9X7958
Datasheet

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