W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet
W83627UHG
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W83627UHG Summary of contents
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... W83627UHG NUVOTON LPC I/O Date: September 17, 2008 Revision: 1.44 Publication Release Date: March 24, 2008 -I- Revision 1.44 ...
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TABLE OF CONTENTS – 1. GENERAL DESCRIPTION ......................................................................................................... 1 2. FEATURES ................................................................................................................................. 2 3. BLOCK DIAGRAM ...................................................................................................................... 5 4. PIN LAYOUT............................................................................................................................... 1 5. PIN DESCRIPTION..................................................................................................................... 2 5.1 LPC Interface ........................................................................................................................ 3 5.2 FDC Interface........................................................................................................................ 3 5.3 Multi-Mode Parallel Port........................................................................................................ 5 ...
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Combination Sensor Data Format...............................................................................................31 7.4.2.1. Temperature Data Format................................................................................................31 7.4.2.2. Voltage Data Format ........................................................................................................32 7.5 PECI.................................................................................................................................... 33 7.6 Fan Speed Measurement and Control................................................................................ 35 7.6.1 Fan Speed Measurement............................................................................................................35 7.6.2 Fan Speed Control ......................................................................................................................35 TM 7.6.3 SMART FAN Control ...............................................................................................................37 TM ...
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Reserved Registers - Index 15h (Bank 0)........................................................................... 59 8.25 Reserved Registers - Index 16h (Bank 0)........................................................................... 59 8.26 Reserved Registers - Index 17h (Bank 0)........................................................................... 59 8.27 OVT# Configuration Register - Index 18h (Bank 0) ............................................................ 59 8.28 Reserved ...
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CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 1) ............................ 76 8.71 CPUTIN/PECI Temperature (Low Byte) Register - Index 51h (Bank 1) ............................. 76 8.72 CPUTIN Configuration Register - Index 52h (Bank 1)........................................................ 76 8.73 CPUTIN Hysteresis (High ...
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UART PORT ........................................................................................................................... 106 10.1 Universal Asynchronous Receiver/Transmitter (UART ......................... 106 10.2 Register Address .............................................................................................................. 106 10.2.1 UART Control Register (UCR) (Read/Write)............................................................................106 10.2.2 UART Status Register (USR) (Read/Write) .............................................................................109 10.2.3 Handshake Control Register ...
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KB Control Register (Logic Device 5, CR-F0)..........................................................................131 12.5.2 Port 92 Control Register (Default Value = 0x24)......................................................................132 13. POWER MANAGEMENT EVENT........................................................................................... 133 13.1 Power Control Logic.......................................................................................................... 133 13.1.1 PSON# Logic...........................................................................................................................134 13.1.1.1. Normal Operation ..........................................................................................................134 13.1.2 AC Power Failure Resume ......................................................................................................135 ...
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Floppy Disk Drive Timing.........................................................................................................201 18.3.7 UART/Parallel Port ..................................................................................................................203 18.3.7.1. Modem Control Timing ..................................................................................................204 18.3.8 Parallel Port Mode Parameters................................................................................................205 18.3.9 Parallel Port .............................................................................................................................206 18.3.9.1. Parallel Port Timing .......................................................................................................206 18.3.9.2. EPP Data or Address Read Cycle Timing Parameters..................................................206 18.3.9.3. EPP Data ...
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... Figure 7-2 Serial Bus Write to Internal Address Register Followed by the Data Byte .................... 24 Figure 7-3 Serial Bus Read from Internal Address Register........................................................... 25 Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG ........................................... 26 Figure 7-5 Monitoring Temperature from Thermistor...................................................................... 29 Figure 7-6 Monitoring Temperature from Thermal Diode (Voltage Mode)...................................... 29 Figure 7-7 Monitoring Temperature from Thermal Diode ...
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List of Tables Table 6-1 Devices of I/O Base Address .......................................................................................... 17 Table 6-2 Chip (Global) Control Registers ...................................................................................... 20 Table 7-1 Temperature Data Format .............................................................................................. 28 Table 7-2 SST Command Summary ............................................................................................... 31 Table 7-3 Typical Temperature Values ........................................................................................... ...
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... GENERAL DESCRIPTION The W83627UHG is a member of Nuvoton's Super I/O product line. This family features the LPC (Low Pin Count) interface. This interface is more economical than its ISA counterpart because it has approximately forty pins fewer, yet still provides as great performance. In addition, the improvement allows even more efficient operation of software, BIOS and device drivers ...
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... Maximum baud rate for clock source 14.769 MHz 921K bps. The baud rate at 24 MHz is 1.5M bps. Parallel Port Compatible with IBM parallel port Support PS/2-compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification W83627UHG Publication Release Date: March 24, 2008 -2- Revision 1.44 ...
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... Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps • Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps TM firmware F MART III functions MART AN TM mode Support Publication Release Date: March 24, 2008 -3- W83627UHG “Thermal Cruise ” Revision 1.44 ...
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... SST temperature and voltage Combination Sensor command support Support SST 0.9 Specification PECI Interface PECI Host Support PECI 1.0 Specification Support 4 CPU addresses and 2 domains per CPU address Package 128-pin QFP Pb-free / RoHS W83627UHG Publication Release Date: March 24, 2008 -4- Revision 1.44 ...
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... GPIO I/O pins PECI PECI interface SST SST interface Hardware monitor HM channel and Vref Keyboard/Mouse KBC data and clock Figure 3-1 W83627UHG Block Diagram W83627UHG LPC Interface Floppy drive interface signals FDC UART Serial port A, B,C,D,E,F interface signals A, B, IRRX IR IRTX ...
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... RID#/GP40 124 124 CTSE#/GP57 CTSE#/GP57 125 125 DSRE#/GP56 DSRE#/GP56 126 126 RTSE#/GP55 RTSE#/GP55 127 127 DTRE#/GP54 DTRE#/GP54 128 128 Figure 4-1 W83627UHG Pin Layout VSB VSB Vtt Vtt VSB VSB VBAT VBAT ...
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... Open-drain output pin with 12mA sink capability Open-drain output pin with 24mA sink capability Output pin with 8mA source-sink capability Output pin with 12mA source-sink capability Output pin with 24mA source-sink capability 24 W83627UHG for details. Publication Release Date: March 24, 2008 -2- Revision 1.44 ...
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... UART. Drive Select A. When set to 0, this pin enables disk drive A. This is an open-drain output. UART F Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. Publication Release Date: March 24, 2008 -3- W83627UHG Revision 1.44 ...
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... OD HEAD# 24 Logic 1 = side 0 17 Logic 0 = side 1 Ring Indicator. An active low signal indicates that a ring signal IN RIF being received from the modem or data set. W83627UHG DESCRIPTION This open-drain output determines which disk Publication Release Date: March 24, 2008 -4- Revision 1.44 ...
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... ECP and EPP modes. DESCRIPTION Diskette Change. This signal is active-low at power-on and whenever the diskette is removed. This input pin needs to connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility. General purpose I/O port 6 bit 0. DESCRIPTION Publication Release Date: March 24, 2008 -5- W83627UHG Revision 1.44 ...
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... Clear To Send. This is the modem-control input. The function of IN CTSC# these pins can be tested by reading bit 4 of the handshake status t 109 register. I/OD GP37 General-purpose I/O port 3 bit 7. 12t W83627UHG DESCRIPTION See the description of the parallel port DESCRIPTION Publication Release Date: March 24, 2008 -6- Revision 1.44 ...
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... Motor A On. When set to 0, this pin enables disk drive 0. This is OD MOA open drain output. UART A Request To Send. An active-low signal informs the O RTSA modem or data set that the controller is ready to send data. W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -7- Revision 1.44 ...
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... I/OD GP34 General-purpose I/O port 3 bit 4. 12t UART D Data Terminal Ready. An active-low signal informs the O DTRD# 8 modem or data set that the controller is ready to communicate. 120 I/OD GP44 General-purpose I/O port 4 bit 4. 8t W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -8- Revision 1.44 ...
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... UART B Serial Output. This pin is used to transmit serial data out SOUTB to the communication link IRTX IR Transmitter output. I/OD GP12 General-purpose I/O port 1 bit 2. 8 UART C Serial Output. This pin is used to transmit serial data out 114 O SOUTC 8 to the communication link. W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -9- Revision 1.44 ...
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... I/OD GP10 General-purpose I/O port 1 bit 0. 12t Ring Indicator. An active-low signal indicates that a ring signal is IN 116 RIC# t being received from the modem or data set. W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -10- Revision 1.44 ...
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... General-purpose I/O port 2 bit 1. CASE OPEN Detection. An active-low input from an external device when the case is open. This signal can be latched if pin VBAT is connected to the battery, even if the W83627UHG is turned off. Pull up a 2-MΩ resistor to VBAT is recommended if useless. Analog Inputs for voltage measurement (Range 2.048 V) ...
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... CPUFANOUT and SYSFANOUT are default PWM mode. Power LED output. This pin is tri-stated as default. General-purpose I/O port 2 bit 0. DESCRIPTION ® INTEL CPU PECI interface. Connect to CPU. ® INTEL CPU Vtt Power. DESCRIPTION Simple Serial Transport (SST) Interface. Publication Release Date: March 24, 2008 -12- W83627UHG Revision 1.44 ...
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... Power LED output. This pin is tri-stated as default.. General-purpose I/O port 2 bit 1. Beep function for hardware monitor. This pin is low after system reset. General-purpose I/O port 2 bit 2. General-purpose I/O port 2 bit 3. Publication Release Date: March 24, 2008 -13- W83627UHG 5VSB 5VCC 5VCC 5VCC 5VCC 5VCC Revision 1.44 ...
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... General-purpose I/O port 2 bit 4. General-purpose I/O port 2 bit 5. Serial Bus clock. General-purpose I/O port 2 bit 6. Serial bus bi-directional data. General-purpose I/O port 2 bit 7. DESCRIPTION Watchdog timer output signal. Suspend-LED output signal. This pin is low as default. DESCRIPTION Publication Release Date: March 24, 2008 -14- W83627UHG Revision 1.44 ...
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... SYMBOL PIN Analog ground. The ground reference for all analog input. AGND 105 Internally connected to all analog circuits. VSS 20,55 Ground. Vtt 89 INTEL W83627UHG DESCRIPTION ® CPU Vtt power. Publication Release Date: March 24, 2008 -15- Revision 1.44 ...
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... CONFIGURATION REGISTER ACCESS PROTOCOL The W83627UHG uses Super I/O protocol to access configuration registers to set up different types of configurations. The W83627UHG has totally fifteen Logical Devices (from Logical Device 0 to Logical Device F with the exception of Logical Device 4 for backward compatibility) corresponding to fifteen individual functions: FDC (Logical Device 0), Parallel Port (Logical Device 1), UARTA (Logical Device 2), UARTB (Logical Device 3), Keyboard Controller (Logical Device 5), UARTC (Logical Device 6), GPIO3, 4 (Logical Device 7), WDTO# & ...
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... FF8h GPIO 3, 4 100h ~ FF8h Reserved GPIO 1, 2 Reserved ACPI Reserved 100h ~ FF8h Reserved UART D 100h ~ FF8h UART E 100h ~ FF8h UART F 100h ~ FF8h Publication Release Date: March 24, 2008 -17- W83627UHG DEFAULT VALUE 3F0h 378h 3F8h 2F8h 60h/64h 3E0h - - - - - - 2E0h 3E8h 2E8h ...
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... N N Extended Function Extended Function Figure 6-2 Configuration Register To program the W83627UHG configuration registers, the following configuration procedures must be followed in sequence: (1). Enter the Extended Function Mode. (2). Configure the configuration registers. (3). Exit the Extended Function Mode. 6.1.1 Enter the Extended Function Mode To place the chip into the Extended Function Mode, two successive writes of 0x87 must be applied to Extended Function Enable Registers (EFERs, i ...
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... DX, 2FH MOV AL, 01H OUT DX select Logical Device 1 ; MOV DX, 2EH MOV AL, F0H OUT DX select CRF0 MOV DX, 2FH MOV AL, 3CH OUT DX update CRF0 with value 3CH ;------------------------------------------ ; Exit the Extended Function Mode ;------------------------------------------ MOV DX, 2EH MOV AL, AAH W83627UHG Publication Release Date: March 24, 2008 -19- Revision 1.44 ...
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... R/W 29h R/W 2Ah R/W 2Bh 2Ch R/W 2Dh R/W 2Eh R/W 2Fh R/W S: Strapping; x: chip version. W83627UHG DEFAULT VALUE DESCRIPTION Software Reset 00h Logical Device A2h Chip ID, MSB 3xh Chip ID, LSB FFh Device Power Down F0h Device Power Down 0100_0ss0b ...
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... The W83627UHG provides hardware access to all monitored parameters through the LPC or I interface and software access through application software, such as Nuvoton’s Hardware Doctor BIOS. In addition, the W83627UHG can generate pop-up warnings or beep tones when a parameter goes outside of a user-specified range. ...
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... CR60 and CR61 accessed using the Super I/O protocol as described in Chapter 6. Due to the number of internal registers necessary to separate the register sets into “banks” specified by register 4Eh. The structure of the internal registers is shown in the following figure. W83627UHG Publication Release Date: March 24, 2008 -22- ...
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... Fan Divisor Registers 59h,5Dh BANK 0 Cirtical Tempature and Curren mode enable 5Eh BANK 0 Smart Fan Configuration Registers 60h~6Ah Publication Release Date: March 24, 2008 -23- W83627UHG BANK 0 FANOUT Critical Temperature 6Bh~6Eh BANK 1 CPUTIN Temperature Control/Stauts Registers 50h~56h BANK 4 Interrupt Status & SMI# Mask Registers ...
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... C interface is a second, parallel port into the internal registers of the hardware monitor function block. The interface is totally compatible with the industry-standard I components that are also compatible to read the internal registers of the W83627UHG hardware monitor and control fan speeds. The address of the I index 48h (which is accessed by the index/data pair at I/O address typically at 295h/296h) ...
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... Serial Bus Address Byte by Master Figure 7-3 Serial Bus Read from Internal Address Register R Ack Frame 2 by 627UHG Internal Index Register Byte R Ack by Frame 4 627UHG Data Byte 0 Publication Release Date: March 24, 2008 -25- W83627UHG Ack by 627UHG Ack Stop by by Master Master Revision 1.44 ...
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... R THM 10K@25 C, beta=3435K Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG As illustrated in the figure above, other connections may require some external circuits. The rest of this section provides more information about voltages outside the range of the 8-bit ADC, CPU Vcore voltage detection, and temperature measurement 7 ...
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... V. The W83627UHG uses the same approach. Pins 12 and 48 provide two functions. One, these pins are connected to 5VCC supply internal (digital / analog) power to the W83627UHG. Two, these pins monitor 5VCC. The voltage value detected on Pin 12 and 48 can be calculated via the equation below: 5VCC Pin 61 is implemented likewise to monitor its +5 V stand-by power supply ...
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... FFh 1,1111,1110 E7h 1,1100,1110 C9h 1,1001,0010 R 10K, 1% VREF Pin 102 CPUTIN Pin 103 SYSTIN Pin 104 Publication Release Date: March 24, 2008 -28- W83627UHG 9-BIT HEX 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h W83627UHG Revision 1.44 ...
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... Monitor Temperature from Thermal Diode (Voltage Mode) The thermal diode D- pin is connected to AGND (pin 105), and the D+ pin is connected to the temperature sensor pin in the W83627UHG. A 15-KΩ resistor is connected to VREF to supply the bias current for the diode, and the 2200-pF, bypass capacitor is added to filter high-frequency noise. The configuration registers to select a thermal diode temperature sensor and the measurement method are found at Bank 0, Index 59h, 5Dh, and 5Eh ...
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... SST Command Summary The W83627UHG can act as an SST peripheral or slave and output the results of the Analog to Digital Converter onto the SST bus. SST is a new, popular standard to communicate temperature and voltage information from around the PC motherboard to report on the status of the system and control cooling fans and other safety mechanisms ...
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... Combination Sensor Data Format 7.4.2.1. Temperature Data Format The W83627UHG temperature data format of both CPUTIN and SYSTIN is 16-bit two’s-complement binary value. It represents multiple of 1/64°C in the temperature reading. Table 1 shows some typical temperature values in 16-bit two’s complement format. ...
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... Voltage Data Format The W83627UHG can return five (5) voltage values through the SST interface. The voltage data format is 16-bit two’s-complement binary. The relation between the 2-byte data and the monitored voltage is listed below: 1) CPUVCORE (pin 101) = Decimal[2-byte data by GetVoltVccp 1024 volts 2) 5VCC (pin 12) = Decimal[2-byte data by GetVolt5V()] / 1024 volts 3) “ ...
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... Calculate TBase. For example, if PECI = -10 and the digital thermometer is 50’C, then TBase could be set to 60’C. (60 – 50). 6. There are two temperature reading registers in the W83627UHG: Bank1, Index 50h & 51h, and Bank2, Index 50h & 51h. The source of the Bank 1, Index 50h & 51h value is determined by the value programmed into the CPUFANOUT monitor Temperature source select register (Hardware Monitor Device, Bank 0, Index 49h, bits (2..0)). The source of Bank 2, Index 50h & ...
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... A warning flag register at Logical Device C, CR[E8h] bit (7..4) is designed for each PECI Agent to report whether the W83627UHG (PECI host) detects the PECI client or not and whether the PECI client returns invalid FCS values from the polling for three successive times. ...
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... This section is divided into two parts, one to measure the speed and the other to control the speed. 7.6.1 Fan Speed Measurement The W83627UHG can measure fan speed for fans equipped with tachometer outputs. The tachometer signals should be set to TTL-level, and the maximum input voltage cannot exceed + the tachometer signal exceeds + external trimming circuit should be added to reduce the voltage accordingly ...
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... The W83627UHG has two output pins for fan control, each of which offers PWM duty cycle and DC voltage to control the fan speed. The output type (PWM or DC) of each pin is configured by Bank0 Index 04h, bits For PWM, the duty cycle is programmed by eight-bit registers at Bank0 Index 01h and Index 03h. The ...
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... TM 7.6 Control MART AN The W83627UHG supports two S MART TM TM Cruise mode—and S F MART features are enabled, fan output starts from the previous setting in Bank0 Index 01h MART AN and Index 03h. There are two pairs of temperature sensors and fan outputs in S figure below. ...
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... BIOS by a fan speed count (the amount of time between clock input signals, not the number of clock input signals in a period of time) and an interval (e.g., 160 ± 10). As long as the fan speed count is in the specified range, fan output remains the same. If the fan speed count is higher than the high end W83627UHG TM mode. ...
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... FAN UP VALUE VALUE OUTPUT VALUE Bank0, Bank0, Bank0, 0Ah 08h 12h, Bit5 Publication Release Date: March 24, 2008 -39- W83627UHG BIT DATA 8 MSB, 1°C bit 7, 0.5 °C 8 MSB, 1°C Bits 7-0 CPUFANOUT Value Bits 7-0 SYSFANOUT Value Mode STEP- STOP STEP- DOWN TIME ...
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... OUTPUT VALUE Bank0, Index 07h Bank0, Index 12h Bits 0-3 Bit5 Bank0, Index 07h Bank0, Index 12h Bits 4-7 Bit4 Pin 90 CPUFANOUT Publication Release Date: March 24, 2008 -40- W83627UHG STEP- STOP STEP- DOWN TIME UP TIME TIME STEP- STEP- DOWN UP TIME TIME Bank0, ...
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... Tar. + Tol. Tar. + Tol III MART AN Tolerance Tolerance Tar 1 Tar 1 Tar 3 Tar 3 Tar Tar Tar 2 Tar 2 Tar 5 Tar 5 Tar 4 Tar 4 III Mechanism (Current Temp. > Target Temp. + Tol.) Publication Release Date: March 24, 2008 -41- W83627UHG Temperature Temperature Step Step Temperature Temperature Revision 1.44 ...
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... The following tables show the current temperature, fan output value and the relative control registers III mode. MART AN Tar Tar Tar 2 Tar 2 Tar 1 Tar 1 III Mechanism (Current Temp. < Target Temp. – Tol.) Publication Release Date: March 24, 2008 -42- W83627UHG Tol . Temperature Temperature Revision 1.44 ...
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... Index 09h STEP DOWN STEP UP TIME TIME Bank0, Index Bank0, 0Fh Index 0Eh Publication Release Date: March 24, 2008 -43- W83627UHG BIT DATA 8 MSB, 1°C bit 7, 0.5 °C Bits 7-0 CPUFANOUT Value MAX. FAN STOP OUTPUT TIME Bank0, Index Bank0, ...
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... In this mode, the SMI# pin can create an interrupt as long as the current temperature exceeds T (Over Temperature). This interrupt can be reset by reading all the interrupt status registers, or Fan Count limit SMI (Temperature Hysteresis) to 127°C. HYST Publication Release Date: March 24, 2008 -44- W83627UHG * * O Revision 1.44 ...
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... Hysteresis) lower than T HYST . Once the temperature rises above T HYST , until the temperature falls below T (Temperature Hysteresis) lower than T HYST , however, and generates an interrupt, this mode does not O Publication Release Date: March 24, 2008 -45- W83627UHG * * * and setting Bank0 however This interrupt must be ...
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... HYST SMI Once the temperature rises above T HYST , until the temperature falls below T O Publication Release Date: March 24, 2008 -46- W83627UHG O . HYST * * This interrupt must be HYST Revision 1.44 ...
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... Pin 74 (VBAT) or Pin 61 (5VSB). 5VSB is the default * * and has not yet fallen below Once the temperature rises above T HYST . This interrupt must be reset by reading all HYST Publication Release Date: March 24, 2008 -47- W83627UHG * . The OVT# pin is HYST . HYST O , however, and O Revision 1.44 ...
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... STATUS Figure 7-22 Caseopen Mechanism 7.7.4 BEEP Alarm Function The W83627UHG provides an alarm output function at the BEEP/GP21 pin. The BEEP/GP21 pin is a multi-function pin and can be configured as BEEP output, if Logical Device B, CR[F2h], bit 1 is set to zero. The BEEP outputs a warning tone when one of the monitored parameters in the following events is out of the preset range ...
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... BEEP/GP21 is an open-drain output pin and its default state is low. When the BEEP alarm function is activated, this pin repeatedly outputs 600 Hz square wave for 0.5 second and 1.2 KHz square wave for 0.5 second in turn until the enable bit or the abnormal event is cleared. W83627UHG Publication Release Date: March 24, 2008 -49- ...
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... DEFAULT 8.2 Data Port (Port x6h) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7-0 Data to be read from written to Value RAM and Register DATA DESCRIPTION 00h (Address Pointer DATA DESCRIPTION Publication Release Date: March 24, 2008 -50- W83627UHG Revision 1.44 ...
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... The PWM duty cycle is equal to this 8-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0%. Strap by FAN_SET (Pin 119) SYSFANOUT voltage control. The output voltage is calculated according equation: Publication Release Date: March 24, 2008 -51- W83627UHG ∗ Divider 256 1 ...
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... PWM output frequency. PWM output frequency = The maximum value of the divider is 127 (7Fh), and it should not be set FANOUT AVCC * OUTPUT Voltage = 64 Strap by FAN_SET (Pin 119 PWM_SCALE2 DESCRIPTION Input Clock 1 ∗ Pre_Scale Divider 256 Publication Release Date: March 24, 2008 -52- W83627UHG Revision 1.44 ...
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... Strap by FAN_SET (Pin 119) CPUFANOUT Voltage Control. The output voltage is calculated according to this equation: FANOUT AVCC * OUTPUT Voltage = 64 Strap by FAN_SET (Pin 119 SYSFAMOUT_MODE CPUFANOUT_SEL DESCRIPTION TM Mode. TM Mode III Mode. MART AN TM Mode. Publication Release Date: March 24, 2008 -53- W83627UHG Reserved 1 0 SYSFANOUT_SEL 0 1 Revision 1.44 ...
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... CPUTIN Target Temperature / CPUFANIN Target Speed 0 0 DEFAULT FUNCTION MODE TM Thermal Cruise DESCRIPTION MART AN III DEFAULT Fan Speed DESCRIPTION TM Cruise DEFAULT DESCRIPTION TM Mode Reserved SYSTIN Target Temperature SYSFANIN Target Speed Reserved CPUTIN Target Temperature CPUFANIN Target Speed Publication Release Date: March 24, 2008 -54- W83627UHG Revision 1.44 ...
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... This value should not be zero Tolerance of CPUTIN Target Tolerance of SYSTIN Target Temperature Temperature Tolerance of CPUFANIN Tolerance Target Speed Target Speed SYSFANOUT Stop Value CPUFANOUT Stop Value III mode, the CPUFANOUT value decreases to this eight- AN Publication Release Date: March 24, 2008 -55- W83627UHG SYSFANIN Revision 1.44 ...
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... Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT TM In Thermal Cruise mode, CPUFANOUT value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan SYSFANOUT Start-up Value CPUFANOUT Start-up Value Publication Release Date: March 24, 2008 -56- W83627UHG Revision 1.44 ...
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... FANOUT to decrease its MART AN value by one step. (1)For PWM output SYSFANOUT Stop Time CPUFANOUT Stop Time III mode, this register determines the amount of time FANOUT Value Step Down Time Publication Release Date: March 24, 2008 -57- W83627UHG Revision 1.44 ...
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... CPUFANOUT value decreases to zero when the temperature goes below the target range. 1: CPUFANOUT value decreases to the value specified in Index 09h when the temperature goes below the target range FANOUT Value Step Up Time CPUFANOUT_MIN_VALUE 0 0 DESCRIPTION Publication Release Date: March 24, 2008 -58- W83627UHG RESERVED Revision 1.44 ...
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... RESERVED. 8.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0) 8.29 Value RAM ⎯ Index 20h ~ 3Fh (Bank 0) ADDRESS A6-A0 20h CPUVCORE reading 21h VIN0 reading 22h AVCC reading DESCRIPTION RESERVED OVT1_MODE DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -59- W83627UHG RESERVED Revision 1.44 ...
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... Note the number of counts of the internal clock for the Low Limit of the fan speed. CPUFANIN Fan Count Limit 3Ch Note the number of counts of the internal clock for the Low Limit of the fan speed. 3Dh Reserved 3Eh Reserved 3Fh Reserved W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -60- Revision 1.44 ...
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... START. A one enables startup of monitoring operations. A zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit INT_CLEAR RESERVED DESCRIPTION Publication Release Date: March 24, 2008 -61- W83627UHG 1 0 SMI#ENABLE START 1 1 Revision 1.44 ...
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... VIN2. A one indicates the high or low limit of VIN2 has been exceeded. 1 RESERVED. 0 VIN1. A one indicates the high or low limit of VIN1 has been exceeded CPUTIN SYSTIN 5VCC AVCC DESCRIPTION CASEOPEN RESERVED VIN2 DESCRIPTION Publication Release Date: March 24, 2008 -62- W83627UHG 1 0 VIN0 CPUVCORE RESERVED VIN1 mode. TM mode. Revision 1.44 ...
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... Interrupt Status Register 1 – Index 41h (Bank 0)). CASEOPEN RESERVED DESCRIPTION A one disables the corresponding interrupt status bit for the SMI interrupt. (Please see Interrupt Status Register 2 – Index 42h (Bank 0)). Publication Release Date: March 24, 2008 -63- W83627UHG 1 0 VIN0 CPUVCORE VIN2 VIN1 Revision 1.44 ...
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... BIT NAME RESERVED 0 0 DEFAULT BIT 7 RESERVED (Read Only RESERVED DESCRIPTION SYFANIN SYSFANIN DIV_B1 DIV_B0 DESCRIPTION Please see Register – Index 5Dh (Bank 0 SERIAL BUS ADDRESS DESCRIPTION Publication Release Date: March 24, 2008 -64- W83627UHG RESERVED VBAT Monitor Control Revision 1.44 ...
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... CPUFANOUT TEMP_SEL[1]. 0 CPUFANOUT TEMP_SEL[0]. 8.40 SYSFANOUT monitor Temperature source select register - Index 4Ah (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT SYSFANOUT SYSFANOUT NAME TEMP_SEL[2] TEMP_SEL[1] W83627UHG DESCRIPTION CPUFANOUT CPUFANOUT TEMP_SEL[2] TEMP_SEL[ DESCRIPTION CPUFANOUT Temperature Source Select. Bits Select CPUTIN as CPUFANOUT Monitor Source. ...
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... Reserved Reserved Select PECI Agent 1 as SYSFANOUT monitor source Select PECI Agent 2 as SYSFANOUT monitor source Select PECI Agent 3 as SYSFANOUT monitor source Select PECI Agent 4 as SYSFANOUT monitor source ADCOVSEL RESERVED DESCRIPTION Publication Release Date: March 24, 2008 -66- W83627UHG Revision 1.44 ...
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... FAN IN/OUT Control Register - Index 4Dh (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME RESERVED 1 0 DEFAULT BIT 7-4 RESERVED. DESCRIPTION EN_T1_ONE RESERVED DIS_OVT2 DESCRIPTION FANOPV2 FANINC2 DESCRIPTION Publication Release Date: March 24, 2008 -67- W83627UHG OVTPOL RESERVED FANOPV1 FANNC1 0 1 Revision 1.44 ...
Page 83
... Pin 113 generates a logic-low signal. (Default) 0 FANINC1 (SYSFANIN Input Control). 1: Pin 113 (SYSFANIN) acts as a FAN tachometer input. (Default) 0: Pin 113 acts as a FAN control signal, and the output value is set by bit 1. W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -68- Revision 1.44 ...
Page 84
... Vendor ID High-Byte, if Index 4Eh, bit7 is 1. Default 5Ch. 7-0 Vendor ID Low Byte, if Index 4Eh, bit Default A3h. 8.46 Reserved Register - Index 50h ~ 55h (Bank RESERVED BANKSEL2 DESCRIPTION VIDL VIDH DESCRIPTION Publication Release Date: March 24, 2008 -69- W83627UHG 1 0 BANKSEL1 BANKSEL0 Revision 1.44 ...
Page 85
... CPUVCORE if the monitored value exceeds the limit EN_ EN_ EN_ EN_ CPUTIN SYSTIN 5VCC AVCC _BP _BP _BP _BP DESCRIPTION 1: Enable BEEP output. 0: Disable BEEP output. (Default) Publication Release Date: March 24, 2008 -70- W83627UHG 1 0 EN_ EN_ VIN0 CPUVCORE _BP _BP 0 0 Revision 1.44 ...
Page 86
... Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT BIT 7-0 Nuvoton Chip ID Number. Default C1h. 8.50 Diode Selection Register - Index 59h (Bank 0) Attribute: Read/Write Size: 8 bits EN_CASEOPEN_BP RESERVED DESCRIPTION CHIPID DESCRIPTION Publication Release Date: March 24, 2008 -71- W83627UHG 1 0 EN_VIN2_BP EN_VIN1_BP Revision 1.44 ...
Page 87
... Enable battery voltage monitor. When this bit changes from zero to one, it takes one monitor cycle time to update the VBAT reading value register. 0: Disable battery voltage monitor SELPIIV2 SELPIIV1 DESCRIPTION SYSFANIN RESERVED DIODES2 DIV_B2 DESCRIPTION Publication Release Date: March 24, 2008 -72- W83627UHG RESERVED EN_ DIODES1 VBAT_MNT Revision 1.44 ...
Page 88
... Reserved Register - Index 5Fh (Bank 0) 8.55 Reserved Registers - Index 60h (Bank 0) 8.56 Reserved Registers - Index 61h (Bank 0) BIT 2 BIT 1 BIT EN_CPUTIN EN_SYSFANOUT RESERVED CURRENT CRITICAL TEMP MODE 0 0 DESCRIPTION Publication Release Date: March 24, 2008 -73- W83627UHG FAN DIVISOR 128 EN_SYSTIN CURRENT RESERVED MODE Revision 1.44 ...
Page 89
... Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT III mode, the CPUFANOUT value increases to this value. This value cannot be zero, MART AN and it cannot be lower than the CPUFANOUT Stop value CPUFANOUT Max. Value Publication Release Date: March 24, 2008 -74- W83627UHG Revision 1.44 ...
Page 90
... CPUFANOUT critical temperature is enabled and monitor temperature over the critical temperature then CPUFANOUT will full drive. 8.68 Reserved Registers - Index 6Dh (Bank 0) 8.69 Reserved Registers - Index 6Eh (Bank CPUFANOUT STEP SYSFANOUT CRITICAL TEMPERATURE CPUFANOUT CRITICAL TEMPERATURE Publication Release Date: March 24, 2008 -75- W83627UHG Revision 1.44 ...
Page 91
... FAULT. Number of faults to detect before setting OVT# output. This avoids false tripping due to noise. 2 RESERVED. This bit should be set OVT2_MODE. OVT# mode select. 0: Compared mode. (Default TEMP<8:1> DESCRIPTION RESERVED DESCRIPTION FAULT RESERVED DESCRIPTION Publication Release Date: March 24, 2008 -76- W83627UHG OVT2_MODE STOP 0 0 Revision 1.44 ...
Page 92
... THYST<0>. Hysteresis temperature bit 0. The nine-bit value is in units of 0.5 6-0 RESERVED. 8.75 CPUTIN Over-temperature (High Byte) Register - Index 55h (Bank1) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 1 DEFAULT DESCRIPTION THYST<8:1> DESCRIPTION RESERVED DESCRIPTION TOVF<8:1> Publication Release Date: March 24, 2008 -77- W83627UHG ° C, and ° Revision 1.44 ...
Page 93
... See SYSFANOUT monitor Temperature source select register – Index 4Ah(Bank 0) ) 8.78 SYSTIN/CPUTIN/PECI Temperature (Low Byte) Register – Index 51h (Bank 2) Attribute: Read Only Size: 8 bits 7 6 BIT NAME TEMP<0> BIT DESCRIPTION RESERVED DESCRIPTION TEMP<8:1> DESCRIPTION RESERVED DESCRIPTION Publication Release Date: March 24, 2008 -78- W83627UHG ° C, and the ° Revision 1.44 ...
Page 94
... A one indicates the high or low limit of 5VSB has been exceeded. 8.85 SMI# Mask Register 4 – Index 51h (Bank 4) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7-2 RESERVED. DESCRIPTION RESERVED DESCRIPTION RESERVED DESCRIPTION Publication Release Date: March 24, 2008 -79- W83627UHG 1 0 VBAT 5VSB VBAT 5VSB 1 1 Revision 1.44 ...
Page 95
... NAME 0 0 DEFAULT DESCRIPTION A one disables the corresponding interrupt status bit for the SMI interrupt. (Please see Interrupt Status Register 3 – Index 50h (Bank 4)). EN_ RESERVED DESCRIPTION OFFSET<7:0> Publication Release Date: March 24, 2008 -80- W83627UHG 1 0 EN_ EN_ VBAT_BP 5VSB_BP Revision 1.44 ...
Page 96
... Fan speed count is over the limit value. 0: Fan speed count is in the allowed range. 5 CPUTIN_STS. 1: Temperature exceeds the over-temperature value. DESCRIPTION OFFSET<7:0> DESCRIPTION CPUTIN SYSTIN 5VCC AVCC _STS _STS _STS _STS DESCRIPTION Publication Release Date: March 24, 2008 -81- W83627UHG VIN0 CPUVCORE _STS _STS 0 0 Revision 1.44 ...
Page 97
... SYSTIN temperature has not reached the warning range. 5 RESERVED. 4 CASEOPEN_STS. Caseopen Status. 1: Caseopen is detected and latched. 0: Caseopen is not latched. 3-1 RESERVED. 0 VIN1_STS. VIN1 Voltage Status. 1: VIN1 voltage is over or under the allowed range. DESCRIPTION RESERVED CASEOPEN_STS DESCRIPTION mode. mode. Publication Release Date: March 24, 2008 -82- W83627UHG RESERVED VIN1_STS Revision 1.44 ...
Page 98
... Index 5Dh, bit0) is set. 52h Reserved 53h Reserved 54h 5VSB High Limit 55h 5VSB Low Limit 56h VBAT High Limit 57h VBAT Low Limit 58h Reserved DESCRIPTION RESERVED DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -83- W83627UHG 1 0 VBAT_STS 5VSB_STS 0 0 Revision 1.44 ...
Page 99
... ADDRESS A6-A0 59h Reserved 5Ah Reserved 5Bh Reserved 5Ch Reserved 8.97 Reserved Register - Index 50h - 57h (Bank 6) W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -84- Revision 1.44 ...
Page 100
... FLOPPY DISK CONTROLLER 9.1 FDC Functional Description The floppy disk controller (FDC) of the W83627UHG integrates all of the logic required for floppy disk control. The FDC implements a FIFO, which provides better system performance in multi-master systems, and the digital data separator supports data rates bits/sec. ...
Page 101
... A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. Perpendicular mode requires a 1 Mbps data rate for the FDC, and, at this data rate, the FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the disk. W83627UHG Publication Release Date: March 24, 2008 -86- Revision 1.44 ...
Page 102
... FDC Core The W83627UHG FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor, and the result may be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. ...
Page 103
... HDS DS1 DS0 Publication Release Date: March 24, 2008 -88- W83627UHG REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution REMARKS Command codes Sector ID information prior to command execution ...
Page 104
... EOT Status information after command execution Sector ID information after command execution Publication Release Date: March 24, 2008 -89- W83627UHG REMARKS Data transfer between the FDD and system Status information after command execution Sector ID information after command execution REMARKS ...
Page 105
... Publication Release Date: March 24, 2008 -90- W83627UHG REMARKS Command codes The first correct ID information on the cylinder is stored in the Data Register Status information after command execution Disk status after the command has been completed REMARKS Command codes Sector ID information prior to command execution No data transfer takes ...
Page 106
... HDS DS1 DS0 Publication Release Date: March 24, 2008 -91- W83627UHG REMARKS Command codes Sector ID information prior to Command execution Data transfer between the FDD and system Status information after Command execution Sector ID information after Command execution REMARKS Command codes Sector ID information prior to command execution ...
Page 107
... Command code Status information at the end of each seek operation Command codes Publication Release Date: March 24, 2008 -92- W83627UHG REMARKS Command codes Bytes per Sector Sectors per Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution REMARKS REMARKS REMARKS Revision 1.44 ...
Page 108
... Command codes 0 0 HDS DS1 DS0 Head positioned over proper cylinder on diskette Configure information Internal registers written HDS DS1 DS0 GAP GAP WG Publication Release Date: March 24, 2008 -93- W83627UHG REMARKS REMARKS REMARKS Command codes REMARKS Registers placed in FIFO REMARKS Command Code Revision 1.44 ...
Page 109
... Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- 9.2 Register Descriptions There are several status, data, and control registers in the W83627UHG. These registers are defined below, and the rest of this section provides more detail about each one of them. ADDRESS OFFSET base address + 0 base address + 1 ...
Page 110
... HEAD#. Indicates the value of the HEAD# output. 0: Side 1. 1: Side 0. 2 INDEX. Indicates the complement of the INDEX# output. 1 WP. 0: The disk is not write-protected STEP TRAK0# HEAD INDEX DESCRIPTION STEP F/F TRAK0 HEAD# INDEX DESCRIPTION Publication Release Date: March 24, 2008 -95- W83627UHG WP# DIR DIR Revision 1.44 ...
Page 111
... WD F/F. Indicates the complement of the WD# output pin, which is latched on every rising edge of the WD# output pin. 3 RDATA F/F. Indicates the complement of the latched RDATA# output pin. DESCRIPTION Drive WDTA RDTA WE SEL0 Toggle Toggle DESCRIPTION RDATA DSA# WD F/F WE F/F F DESCRIPTION Publication Release Date: March 24, 2008 -96- W83627UHG 1 0 MOT EN MOT DSD# DSC Revision 1.44 ...
Page 112
... In normal floppy mode, this register only has bits 0 and 1, and the bit definitions are as follows BIT NAME NA NA DEFAULT BIT DESCRIPTION MOTOR DMA&INT FDC ENABLE A ENABLE RESET DESCRIPTION RESERVED DESCRIPTION Publication Release Date: March 24, 2008 -97- W83627UHG 1 0 DRIVE SELECT Tape sel 1 Tape sel Revision 1.44 ...
Page 113
... Drive 0 is not available as a tape drive and is reserved for the floppy disk boot drive. TAPE SEL 0 DRIVE SELECTED Non-DMA FDD 3 FDD 2 FDC Busy mode Busy Busy Publication Release Date: March 24, 2008 -98- W83627UHG Tape Sel Tape Sel None FDD 1 FDD 0 Busy Busy Revision 1 ...
Page 114
... PRECOMP 2. 3 PRECOMP 1. 2 PRECOMP DESCRIPTION PRECOMP2 PRECOMP1 PRECOMP0 DESCRIPTION Selects the value of write precompensation. The following precompensation combination of these bits. Please see the tables below. Publication Release Date: March 24, 2008 -99- W83627UHG DRATE1 DRATE0 tables show the values for every Revision 1.44 ...
Page 115
... The FIFO register stores data, commands, and parameters, and it provides disk- drive status information. In addition, data bytes pass through the data register to program or obtain results after a command. In the W83627UHG, this register is disabled after reset. The FIFO can enable it and change its values through the configure command. ...
Page 116
... EN (End of Track). 1 will be written to this bit if the FDC tries to access a sector beyond the final sector or a cylinder. 6 Not Used. This bit is always Not HD Head Equipment End Ready Address Check DESCRIPTION Not Used ND DESCRIPTION Publication Release Date: March 24, 2008 -101- W83627UHG 1 0 US1, US0 Drive Select MAM Revision 1.44 ...
Page 117
... Bad Cylinder error (Missing Address Mark in Data Field FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media error. Status Register 3 (ST3) DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -102- W83627UHG Revision 1.44 ...
Page 118
... Always 1 during a read. 2 DRATE DESCRIPTION RESERVED DESCRIPTION DRATE1 DESCRIPTION Select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for Publication Release Date: March 24, 2008 -103- W83627UHG 1 0 US1 US0 HIGH DRATE0 DENS Revision 1.44 ...
Page 119
... RESERVED NA NAN NA NA DESCRIPTION Select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4) for Publication Release Date: March 24, 2008 -104- W83627UHG 1 0 DRATE1 DRATE0 DRATE1 DRATE0 1 0 Revision 1.44 ...
Page 120
... NOPREC DESCRIPTION Select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates. Publication Release Date: March 24, 2008 -105- W83627UHG 1 0 DRATE1 DRATE0 1 0 Revision 1.44 ...
Page 121
... MSBE (Multiple Stop Bit Enable). Defines the number of stop bits in each serial character that is transmitted or received. (1) If MSBE is set to logic 0, one stop bit is sent and checked PBFE EPE PBE MSBE DESCRIPTION Publication Release Date: March 24, 2008 -106- W83627UHG 1 0 DLS1 DLS0 0 0 Revision 1.44 ...
Page 122
... DLS0 (Data Length Select Bit 0). Defines the number of data bits that are sent or checked in each serial character. DLS1 The following table identifies the remaining UART registers. Each one is described separately in the following sections. DESCRIPTION DLS0 DATA LENGTH Publication Release Date: March 24, 2008 -107- W83627UHG 5 bits 6 bits 7 bits 8 bits Revision 1.44 ...
Page 123
... RI Falling DCD Toggling Edge Toggling (TDSR) (FERI) (TDCD) Bit 1 Bit 2 Bit 3 Bit 1 Bit 2 Bit 3 Bit 9 Bit 10 Bit 11 Publication Release Date: March 24, 2008 -108- W83627UHG Data RX Data RX Data RX Data Bit 4 Bit 5 Bit 6 Bit 7 TX Data TX Data TX Data TX Data Bit 4 Bit 5 Bit 6 Bit 7 ...
Page 124
... RDR (RBR Data Ready). This bit is set to logical 1 to indicate that the received data are ready to be read by the CPU in the RBR or FIFO. When no data are left in the RBR or FIFO, the bit is set to logical TBRE SBD NSER PBER DESCRIPTION Publication Release Date: March 24, 2008 -109- W83627UHG 1 0 OER PDR 0 0 Revision 1.44 ...
Page 125
... DCD (Data Carrier Detect). This bit is the inverse of the DCD# input and is equivalent to bit 3 of HCR in Loopback mode INTERNAL IRQ LOOPBACK LOOPBACK ENABLE RI INPUT ENABLE DESCRIPTION DSR CTS TDCD FERI DESCRIPTION Publication Release Date: March 24, 2008 -110- W83627UHG 1 0 RTS DTR TDSR TCTS NA NA Revision 1.44 ...
Page 126
... These two bits are used to set the active level of the receiver FIFO interrupt. The active level is the number of bytes that must be in the receiver FIFO to generate an interrupt. RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) 01 Publication Release Date: March 24, 2008 -111- W83627UHG 1 0 RECEIVER FIFO FIFO ENABLE RESET 0 0 Revision 1 ...
Page 127
... NSER = 1 4. SBD = 1 1. RBR data ready 2. FIFO interrupt active level reached Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR empty Publication Release Date: March 24, 2008 -112- W83627UHG 1 0 INTERRUPT 0 IF STATUS INTERRUPT BIT 0 PENDING 0 ...
Page 128
... ERDRI (RBR Data Ready Interrupt Enable). Set this bit to logical 1 to enable the RBR data ready interrupt. INTERRUPT SET AND FUNCTION 1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = EHSRI EUSRI DESCRIPTION Publication Release Date: March 24, 2008 -113- W83627UHG Read HSR 1 0 ETBREI ERDRI 0 0 Revision 1.44 ...
Page 129
... PARALLEL PORT 11.1 Printer Interface Logic The W83627UHG parallel port can be attached to devices that accept eight bits of parallel data at standard TTL level. The W83627UHG supports the IBM XT/AT compatible parallel port (SPP), the bi- directional parallel port (BPP), the Enhanced Parallel Port (EPP), and the Extended Capabilities Parallel Port (ECP) ...
Page 130
... PD4 PD3 PD2 PD6 PD5 PD4 PD3 PD2 PD6 PD5 PD4 PD3 PD2 SLCT ERROR DESCRIPTION Publication Release Date: March 24, 2008 -115- W83627UHG NOTE PD1 PD0 1 TMOUT AUTOFD# STROBE# AUTOFD# STROBE# PD1 PD0 PD1 PD0 PD1 PD0 PD1 PD0 PD1 PD0 ...
Page 131
... The leading edge of IOW# causes an EPP address write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. DESCRIPTION DIR IRQ ENABLE SLCT IN INIT DESCRIPTION PD5 PD4 PD3 PD2 Publication Release Date: March 24, 2008 -116- W83627UHG AUTO FD STROBE PD1 PD0 Revision 1.44 ...
Page 132
... During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read cycle to be performed and the data to be output to the host CPU PD5 PD4 PD3 PD2 Publication Release Date: March 24, 2008 -117- W83627UHG 1 0 PD1 PD0 Revision 1.44 ...
Page 133
... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it does not finish until nWait changes from active low to inactive high. W83627UHG EPP DESCRIPTION Publication Release Date: March 24, 2008 -118- Revision 1 ...
Page 134
... Extended Capabilities Parallel (ECP) Port This port is software- and hardware-compatible with existing parallel ports, so the W83627UHG parallel port may be used in standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host-to-peripheral) and reverse (peripheral-to-host) directions ...
Page 135
... R/W 111 Configuration Register B R/W All Extended Control Register PD5 PD4 PD3 PD2 PError Select nFault 1 Directio ackIntEn SelectIn nInit nErrIntrEn dmaEn serviceIntr Publication Release Date: March 24, 2008 -120- W83627UHG FUNCTION D1 D0 NOTE PD1 PD0 Autofd strobe full empty Revision 1.44 ...
Page 136
... The parallel port is in the output mode. 1: The parallel port is in the input mode PD5 PD4 PD3 PD2 Address or RLE PError Select nFault DESCRIPTION Director ackInEn SelectIn nInit DESCRIPTION Publication Release Date: March 24, 2008 -121- W83627UHG 1 0 PD1 PD0 Autofd Strobe NA NA Revision 1.44 ...
Page 137
... CNFGA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates that this is an 8-bit implementation. 11.3.9 CNFGB (Configuration Register B) Mode = 111 The bit definitions are as follows: W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -122- Revision 1.44 ...
Page 138
... NAME 0 0 DEFAULT BIT IRQx2 IRQx1 IRQx0 DESCRIPTION IRQ resource Reflects other IRQ resources selected by PnP register (default) IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRQ5 MODE nErrIntrEn dmaEn ServiceIntr DESCRIPTION Publication Release Date: March 24, 2008 -123- W83627UHG Full Empty Revision 1.44 ...
Page 139
... Full. Read Only. 0: The FIFO has at least one free byte. 1: The FIFO is completely full; it cannot accept another byte. 0 Empty. Read Only. 0: The FIFO contains at least one byte of data. 1: The FIFO is completely empty. W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -124- Revision 1.44 ...
Page 140
... Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. (d) Set mode = 011 (ECP Mode) ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively. DESCRIPTION acknowledge nReverseRequest. Publication Release Date: March 24, 2008 -125- W83627UHG The host relies upon Revision 1.44 ...
Page 141
... PeriphAck is low. The most significant bit of the command is always zero. 11.3.12.3. Data Compression The W83627UHG hardware supports RLE decompression and can transfer compressed data to a peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to ecpDFifo ...
Page 142
... The host must set dmaEn and serviceIntr to 0 and also must set the direction and state accordingly in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O empties or fills the FIFO using the appropriate direction and mode. W83627UHG Publication Release Date: March 24, 2008 -127- Revision 1.44 ...
Page 143
... KEYBOARD CONTROLLER The W83627UHG KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with IBM compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
Page 144
... Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) FUNCTION BIT DEFINITION IBM Keyboard Translate Mode Enable Keyboard Interrupt Publication Release Date: March 24, 2008 -129- W83627UHG Revision 1.44 ...
Page 145
... Output next received byte of data from system to Auxiliary Device E0h Reports the status of the test inputs FXh Pulse only RC (the reset line) low for 6μs if the Command byte is even W83627UHG FUNCTION BIT DEFINITION Publication Release Date: March 24, 2008 -130- Revision 1.44 ...
Page 146
... RESERVED P92EN DESCRIPTION Select the KBC clock rate. Bits KBC clock input is 6 MHz KBC clock input is 8 MHz KBC clock input is 12 MHz KBC clock input is 16 MHz. Publication Release Date: March 24, 2008 -131- W83627UHG 1 0 HGA20 HKBRST Revision 1.44 ...
Page 147
... PLKBRST# (Pulled-low KBRESET). A logical 1 on this bit causes KBRESET to drive low for 6 μS(Min.) with a 14 μS(Min.) delay. Before issuing another keyboard-reset command, the bit must be cleared RES. (1) RES. (0) RES. ( DESCRIPTION Publication Release Date: March 24, 2008 -132- W83627UHG 1 0 SGA20 PLKBRST Revision 1.44 ...
Page 148
... Logical Device A, CR[F2h], bit[0] and is for enabling or disabling the PME function. If this bit is set to “0”, the W83627UHG won’t output any PME signal when any of the wake-up events has occurred and is enabled. The four registers are divided into PME status registers and PME ...
Page 149
... PSOUT# PSOUT# PWRBTN# PWRBTN# PWRBTN# PWRBTN# South Bridge South Bridge South Bridge South Bridge SLP_S3# SLP_S3# SLP_S3# SLP_S3# Publication Release Date: March 24, 2008 -134- W83627UHG PSON# PSON# PSON# PSON# VCC ON VCC ON VCC ON VCC ON VCC ON VCC ON Power Power Power Power Supply Supply ...
Page 150
... AC Power Failure Resume By definition, AC power failure means that the standby power is removed. The power failure resume control logic of the W83627UHG is used to recover the system to a pre-defined state after AC power failure. Two control bits at Logical Device A, CR[E4h], bits[6:5] indicate the pre-defined state. The ...
Page 151
... To ensure that VCC does not fall faster than VSB in various ATX Power Supplies, the W83627UHG adds the option of “user define mode” for the pre-defined state before AC power failure. BIOS can set the pre-defined state to be “On” or “Off”. According to this setting, the system is returned to the pre- defined state after the AC power recovery ...
Page 152
... DEVICE A, (LOGICAL DEVICE CR[E6H], BIT 7) A, CR[E0H], BIT First-pressed key “0” Second-pressed key “1” Third-pressed key “2” MSXKEY (LOGICAL WAKE-UP EVENT DEVICE A, CR[E0H], BIT 1) Any button clicked or any 1 movement. Publication Release Date: March 24, 2008 -137- W83627UHG Revision 1.44 ...
Page 153
... The RSMRST# (Pin 75) signal is a reset output and is used as the 5VSB power on reset signal for the South Bridge. When the W83627UHG detects the 5VSB voltage rises to “V1”, it then starts a delay – “t1” before the rising edge of RSMRST# asserting. If the 5VSB voltage falls below “V2”, the RSMRST# de-asserts immediately ...
Page 154
... When the W83627UHG detects both of the 5VCC and 3VCC voltages rise to “V3” and “V5”, it then starts a delay – “t2” before the rising edge of PWROK assertion. If both of the 5VCC and 3VCC voltages fall below “V4” and “V6”, the PWROK de-asserts immediately. ...
Page 155
... No delay time. 10 For example, if Logical Device A, CR[E6h] bit 2 is set to “0” and bits 2~1 are set to “10”, the range of t2 timing is from 396(300 + 96 596(500 + 96) mS. W83627UHG DEFINITION 01: Delay 32 ms 11: Delay 250 ms Publication Release Date: March 24, 2008 -140- ...
Page 156
... Figure 14-1 Start Frame Timing with Source Sampled A Low Pulse on IRQ1 H=Host Control SL=Slave Control Note: 1. The Start Frame pulse can be 4-8 clocks wide. 2. The first clock of Start Frame is driven low by the W83627UHG because IRQ1 of the W83627UHG IRQ1 FRAME IRQ0 FRAME R T ...
Page 157
... Then the host takes over and continues to pull the SERIRQ low. 14.2 IRQ/Data Frame Once the Start Frame has been initiated, the W83627UHG must start counting frames based on the rising edge of the start pulse. Each IRQ/Data Frame has three clocks: the Sample phase, the Recovery phase, and the Turn-around phase ...
Page 158
... The Start Frame pulse of next SERIRQ cycle may or may not start immediately after the turn-around clock of the Stop Frame CLOCKS PAST START IOCHCK# STOP FRAME FRAME STOP None Host Controller T=Turn-around S=Sample Publication Release Date: March 24, 2008 -143- W83627UHG EMPLOYED NEXT CYCLE START 2 I= Idle. Revision 1.44 ...
Page 159
... The W83627UHG outputs a low signal to the WDTO# pin (pin 77) when a time-out event occurs. In other words, when the value is counted down to zero, the timer stops, and the W83627UHG sets the WDTO# status bit in Logical Device 8, CR[F7h], bit[4], outputting a low signal to the WDTO# pin(pin 77) ...
Page 160
... GENERAL PURPOSE I/O 16.1 GPIO Architecture The W83627UHG provides 45 input/output ports that can be individually configured to perform a simple basic I/O function or an alternative, pre-defined function. GPIO ports 1 ~2 are configured through control registers in Logical Device 9, GPIO ports 3~4 in Logical Device 7, and GPIO ports 5~6 in Logic Device 8 ...
Page 161
... Table 16-2 GPIO Register Addresses ADDRESS ABBR 7 6 GSR Base + 0 IOR Base + 1 DAT Base + 2 INV Base + 3 DST Base + 4 BIT NUMBER Reserved GPIO I/O Register GPIO Data Register GPIO Inversion Register GPIO Status Register Publication Release Date: March 24, 2008 -146- W83627UHG 1 0 INDEX Revision 1.44 ...
Page 162
... UARTE Power Down 0: Powered down 1: Not powered down UARTD Power Down. 0: Powered down 1: Not powered down UARTC Power Down. 0: Powered down 1: Not powered down 3~1 Reserved. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 0: Powered down 1: Not powered down 0: Powered down 1: Not powered down 0: Powered down 1: Not powered down ...
Page 163
... GP64 Pin 7 DSRF# Pin 8 RTSF# Pin 9 DTRF# Pin 10 SINF Pin 11 SOUTF Pin 13 DCDF# Pin 14 GP63 Pin 15 GP62 Pin 16 GP61 W83627UHG DESCRIPTION s: value by strapping DESCRIPTION Enable FDC interface Pin 5 DRVDEN0 Pin 6 INDEX# Pin 7 MOA# Pin 8 DSA# Pin 9 DIR# Pin 10 STEP# Pin 11 WD# ...
Page 164
... Enable PRT legacy mode for IRQ and DRQ selection. Then DCR register (base address + 2) bit 4 is effective when selecting IRQ Disable PRT legacy mode for IRQ and DRQ selection. Then DCR register (base address + 2) bit 4 is not effective when selecting IRQ. W83627UHG Enable FDC interface Pin 17 HEAD# Pin 18 DSKCHG# ...
Page 165
... IRQ. 3 Reserved. PRTMODS2 ~ 0 => 2 0xx Parallel Port Mode. = 1xx Reserved. CR 29h. (OVT#/HM_SMI#, PLED & GPIO3 Output Type Select; Default 00h) BIT READ / WRITE W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -150- Revision 1.44 ...
Page 166
... Disable SCL input to a filter Pin 69, Pin 70 function select ( Pin 69 Pin 69 Reserved. CR 2Bh. (Reserved) CR 2Ch. (GPIO1 Multi-function and GPIO1, 2 Output Type Select; Default 02h) BIT READ / WRITE W83627UHG DESCRIPTION pulse with 50% duty cycle. 4 (VSB Power) DESCRIPTION 2 C interface) GP25, GP26 (Default) SDA, SCL ...
Page 167
... Disable GP25 input de-bouncer. 3 Reserved. 0: GP27 trigger type :edge GP27 trigger type :level 0: GP26 trigger type :edge GP26 trigger type :level 0: GP25 trigger type :edge GP25 trigger type :level W83627UHG DESCRIPTION Bit-0 Pins function Pin 82 Reserved ( tri-state) 0 Pin 83 Reserved ( always low) Others GPIO1 ...
Page 168
... CR 2Eh. (Default 00h) BIT READ / WRITE 7 Test Mode Bits: Reserved. CR 2Fh. (Default 00h) BIT READ / WRITE 7 Test Mode Bits: Reserved. W83627UHG DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -153- Revision 1.44 ...
Page 169
... FDD interface signals are active high. When this bit is logic 0, it indicates a second drive is installed and reflected in status register A. (PS2 mode only) Swap Drive 0, 1 Mode => Swap. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 001: DMA1. 010: DMA2. 011: DMA3. DESCRIPTION 1: Drive and Motor select 0 and 1 are swapped. ...
Page 170
... FDD A Drive Type. CR F4h. (Default 00h) BIT READ / WRITE 7 Reserved. 0: Enable FDC Pre-compensation Disable FDC Pre-compensation. 5 Reserved. W83627UHG DESCRIPTION 00: Model 30. 01: PS/2. 10: Reserved. 11: AT Mode 0: Burst Mode is enabled 1: Non-Burst Mode. 0: Normal Floppy Mode. 1: Enhanced 3-mode FDD. DESCRIPTION 00: FDD A. 01: FDD B. 10: FDD C. ...
Page 171
... DRIVE RATE TABLE DATA RATE SELECT DRTS1 DRTS0 DRATE1 TABLE B DTYPE0 DTYPE1 DRVDEN0 (pin SELDEN W83627UHG DESCRIPTION 10: 2 Meg Tape. 11: Reserved. DESCRIPTION SELECTED DATA RATE DRATE0 MFM FM 1 1Meg --- 0 500K 250K 1 300K 150K 0 250K 125K 1 1Meg --- 0 500K 250K 1 500K 250K 0 250K ...
Page 172
... DTYPE0 DTYPE1 DRVDEN0 (pin DRATE1 1 0 SELDEN 1 1 DRATE0 W83627UHG DRVDEN1 (pin 3) DRIVE TYPE DRATE0 DRATE0 DRATE1 Publication Release Date: March 24, 2008 -157- Revision 1.44 ...
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... ECP mode. 2 011: ECP and EPP – 1.9 mode. 100: Printer Mode. 101: EPP – 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP – 1.7 mode. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 001: DMA1. 010: DMA2. 011: DMA3. DESCRIPTION ...
Page 174
... Reserved. 00: UART A clock source is 1.8462 MHz (24 MHz / 13). 01: UART A clock source is 2 MHz (24 MHz / 12). 1 00: UART A clock source is 24 MHz (24 MHz / 1). 00: UART A clock source is 14.769 MHz (24 MHz / 1.625). W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -159- Revision 1.44 ...
Page 175
... UART B clock source is 1.8462 MHz (24 MHz / 13). 01: UART B clock source is 2 MHz (24 MHz / 12). 1 00: UART B clock source is 24 MHz (24 MHz / 1). 00: UART B clock source is 14.769 MHz (24 MHz / 1.625). CR F1h. (Default 00h) W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -160- ...
Page 176
... Active pulse 1.6 μ S Demodulation into SINB/IRRX Active pulse 3/16 bit time Demodulation into SINB/IRRX KHZ clock Inverting IRTX/SOUTB Demodulation into SINB/IRRX Demodulation into SINB/IRRX KHZ clock DESCRIPTION Publication Release Date: March 24, 2008 -161- W83627UHG IRRX High Routed to SINB/IRRX Routed to SINB/IRRX Revision 1.44 ...
Page 177
... KBC clock rate selection 00: 6MHz 7 01: 8MHz 10: 12MHz 11: 16MHz 5~3 Reserved. 0: Port 92 disabled Port 92 enabled. 0: Gate A20 software control Gate A20 hardware speed up. 0: KBRST# software control KBRST# hardware speeds up. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -162- Revision 1.44 ...
Page 178
... Reserved. 00: UART C clock source is 1.8462 MHz (24 MHz / 13). 01: UART C clock source is 2 MHz (24 MHz / 12). 1 00: UART C clock source is 24 MHz (24 MHz / 1). 00: UART C clock source is 14.769 MHz (24 MHz / 1.625). W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -163- Revision 1.44 ...
Page 179
... Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears E4h. (GPIO4 I/O Register; Default FFh) BIT READ / WRITE W83627UHG DESCRIPTION 1: GPIO4 is active. 1: GPIO3 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -164- Revision 1 ...
Page 180
... READ / WRITE GPIO4 Event Status Bits 7-0 correspond to GP47-GP40, respectively. Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -165- Revision 1.44 ...
Page 181
... The respective bit and the port value are the same. 7 The respective bit and the port value are inverted. (Both Input & Output ports) CR E3h. (Status Register; Default 00h) BIT READ / WRITE W83627UHG DESCRIPTION 1: GPIO6 is active. 1: GPIO5 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 182
... No active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears F5h. (WDTO# and KBC P20 Control Mode Register; Default 00h) BIT READ / WRITE 7~5 Reserved. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -167- ...
Page 183
... Watchdog timer is reset by mouse interrupt. Keyboard interrupt reset watch-dog timer enable Watchdog timer is not affected by keyboard interrupt. 1: Watchdog timer is reset by keyboard interrupt. 5 Write “1” Only Trigger WDTO# event. This bit is self-clearing. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -168- Revision 1.44 ...
Page 184
... BIT READ / WRITE WDTO# status bit Watchdog timer is running. Write “0” Clear 1: Watchdog timer issues time-out event. 3 These bits select IRQ resource for WDTO#. (02h for SMI# event.) W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -169- Revision 1.44 ...
Page 185
... Read Only 7 active edge(rising/falling) has been detected Read-Clear active edge(rising/falling) has been detected Reading the status bit clears E4h. (GPIO2 I/O Register; Default FFh) BIT READ / WRITE W83627UHG DESCRIPTION 1: GPIO2 is active. 1: GPIO1 is active. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -170- Revision 1 ...
Page 186
... READ / WRITE Select Suspend LED mode. 00: Suspend LED pin is driven low. 7 01: Suspend LED pin is tri-stated. 10: Suspend LED pin outputs 1Hz pulse with 50% duty cycle. 11: Suspend LED pin outputs 5~0 Reserved. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION pulse with 50% duty cycle. 4 ...
Page 187
... CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please refer to the following table for the details. ENMDAT_UP MSRKEY Reserved. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION MSXKEY Wake-up event x 1 Any button clicked or movement. One click of either left or right button One click of the MS left button ...
Page 188
... This bit is 1: When power loss occurs and VSB power is on, it indicates that the system power is turned off. If E4[ => This bit is always 0. Thermal shutdown status. Read Only thermal shutdown event is issued. Read-Clear 1: The thermal shutdown event is issued. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -173- Revision 1.44 ...
Page 189
... GPIO 6 reset source control bit Enable GPIO 6 reset source by LRESET# =1 Disable GPIO 6 reset source by LRESET# GPIO 5 reset source control bit Enable GPIO 5 reset source by LRESET# =1 Disable GPIO 5 reset source by LRESET# W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -174- Revision 1.44 ...
Page 190
... Set the delay time when rising from PWROK_ST to PWROK. 2 00: No delay time. 10 PWROK_TRIG => W-Clear Write 1 to re-trigger the PWROK signal from low to high. CR E7h. (Default 00h) W83627UHG DESCRIPTION DESCRIPTION 01: Delay 32 ms 11: Delay 250 ms Publication Release Date: March 24, 2008 -175- Revision 1.44 ...
Page 191
... Hardware Monitor RESET source select (VBAT PWROK. 1: LRESET#. CR E8h. (Reserved) CR E9h. (Reserved.) CR F2h. (Default 3Eh) (VSB Power) BIT READ / WRITE 7~1 Reserved EN_PME => CR F3h. (Default 00h) BIT READ / WRITE W83627UHG DESCRIPTION DESCRIPTION 0: Disable PME. 1: Enable PME. DESCRIPTION Publication Release Date: March 24, 2008 -176- Revision 1.44 ...
Page 192
... R / W-Clear Write 1 to clear this status. CR F6h. (Default 00h) (VSB Power) BIT READ / WRITE 7 Reserved. 0: Disable PME interrupt of the URC IRQ event Enable PME interrupt of the URC IRQ event. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -177- Revision 1.44 ...
Page 193
... Disable GP27 event route to PSOUT Enable GP27 event route to PSOUT#. 0: Disable GP26 event route to PSOUT Enable GP26 event route to PSOUT#. 0: Disable GP25 event route to PSOUT Enable GP25 event route to PSOUT#. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -178- Revision 1.44 ...
Page 194
... Reserved. 0: Disable GP27 event route to PME Enable GP27 event route to PME#. 0: Disable GP26 event route to PME Enable GP26 event route to PME#. 0: Disable GP25 event route to PME Enable GP25 event route to PME#. W83627UHG DESCRIPTION Publication Release Date: March 24, 2008 -179- Revision 1.44 ...
Page 195
... Read Only 0: PIN 107,108 1: PIN 107,108 FAN_SET strapping status. This bit is strapped by pin 119 (RTSD# / GP45). 0 Read Only 0: The initial speed is 100%. 1: The initial speed is 50%. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION BEEP, PLED GP20, GP21 Publication Release Date: March 24, 2008 -180- ...
Page 196
... CR E8 [3] is set to 1, this register is used to read the relative temperature of Agent 1 (Low Byte)). Note. Agent 1 ~ Agent 4 represent the addresses of PECI devices from 0x30h to 0x33h respectively. CR E1h. (Agent 1 TControl Register; Default 48h) BIT READ / WRITE 7 Reserved. W83627UHG DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -181- Revision 1.44 ...
Page 197
... Agt4D1 (Agent 4 Domain 1 Enable Bit Agent 4 does not have domain 1. 1: Agent 4 has domain 1. Agt3D1 (Agent 3 Domain 1 Enable Bit Agent 3 does not have domain 1. 1: Agent 3 has domain 1. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -182- Revision 1.44 ...
Page 198
... Agent 4 cannot be detected. Agent 3 Alert Bit (When CR E8[ Agent 3 has valid FCS. 1: Agent 3 has invalid FCS in the previous 3 transactions Agent 3 Absent Bit (When CR E8[ Agent 3 is detected. 1: Agent 3 cannot be detected. W83627UHG DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -183- Revision 1.44 ...
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... Agent Configuration Register CR E1 Agent 1 TBase Register CR E2 Agent 2 TBase Register CR E3 Agent 3 TBase Register CR E4 Agent 4 TBase Register W83627UHG DESCRIPTION CR E8 BIT Agt1RelTemp (Low Byte) Agt1RelTemp (High Byte) Agt2RelTemp (Low Byte) Agt2RelTemp (High Byte) Agt3RelTemp (Low Byte) Publication Release Date: March 24, 2008 -184- Revision 1 ...
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... Vendor ID to associate the correct software driver with the sensor. Agt3RelTemp (High Byte) Reserved Agt4RelTemp (Low Byte) Reserved Agt4RelTemp (High Byte) DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: March 24, 2008 -185- W83627UHG CR E8 BIT Agent Absent Bit Revision 1.44 ...