W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 119
W83627UHG
Manufacturer Part Number
W83627UHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Specifications of W83627UHG
Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V, 5V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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In PS/2 Model 30 mode, the bit definitions are as follows:
This register is used to control the data rate. In PC/AT and PS/2 mode, the bit definitions are as
follows:
DEFAULT
DEFAULT
9.2.9 Configuration Control Register (CC Register) (Write base address + 7)
NAME
BIT
NAME
BIT
6-4
BIT
7-2
1
0
7
3
2
1
0
1
BIT
BIT
DRATE 0.
HIGHDENS#.
0: 500 KB/S or 1 MB/S data rate (high-density FDD).
1: 250 KB/S or 300 KB/S data rate.
DSKCHG. Indicates the status of the DSKCHG# input.
Always 0 during a read.
DMAEN. Indicates the value of DO register, bit 3.
NOPREC. Indicates the value of the NOPREC bit in the CC REGISTER.
DRATE 1.
DRATE 0.
RESERVED. Should be set to 0.
DRATE 1.
DSKCHG#
NA
7
7
1
NA
6
6
0
NA
5
5
0
RESERVED
DESCRIPTION
DESCRIPTION
DESCRIPTION
NAN
-104-
4
4
0
how the settings correspond to individual
data rates.
Select the data rate of the FDC. See DR
register bits 1 and 0 (Data Rate Register
(DR Register) (Write base address +4)) for
how the settings correspond to individual
data rates.
Select the data rate of the FDC. See DR
register bits 1 and 0 (Data Rate Register
(DR Register) (Write base address + 4) for
DMAEN
NA
3
3
0
Publication Release Date: March 24, 2008
NOPREC
NA
2
2
0
W83627UHG
DRATE1
DRATE1
1
1
1
1
Revision 1.44
DRATE0
DRATE0
0
0
0
0
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