W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 154

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the W83627UHG detects both of the 5VCC and 3VCC voltages rise to “V3” and “V5”, it then
starts a delay – “t2” before the rising edge of PWROK assertion. If both of the 5VCC and 3VCC
voltages fall below “V4” and “V6”, the PWROK de-asserts immediately.
Timing and the voltage parameters are shown in Figure 13-4 and Table 13-4.
Originally, the t2 timing is between 300 mS to 500 mS, but it can be changed to 200 mS to 300 mS by
programming Logical Device A, CR[E6h], bit 3 to “1”. Furthermore, the W83627UHG provides four
different extra delay time of PWROK for various demands. The four extra delay time are designed at
Logical Device A, CR[E6h], bits 2~1. The following table shows the definitions of Logical Device A,
CR[E6h] bits 3 ~1.
NAME
V3
V4
V5
V6
LOGICAL DEVICE A,
PWROK
t2
5VCC
3VCC
CR[E6H] BIT
5VCC Valid Voltage
5VCC Ineffective Voltage
3VCC Valid Voltage
3VCC Ineffective Voltage
Valid 5VCC and 3VCC to PWROK active
3
V3
V5
Table 13-4 Timing and the Voltage Parameters of PWROK
PARAMETER
t2
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to
PWROK_ST.
0: 300 ~ 500 mS.
1: 200 ~ 300 mS.
Figure 13-4 PWROK Generation Mechanism
-139-
DEFINITION
MIN.
300
2.6
2.1
-
-
MAX.
Publication Release Date: March 24, 2008
500
4.3
2.9
-
UNIT
mS
V
V
V
V
V4
V6
W83627UHG
Revision 1.44