W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 7

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.
14.
15.
16.
17.
18.
13.1
13.2
13.3
13.4
14.1
14.2
14.3
16.1
16.2
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
17.10
17.11
17.12
17.13
17.14
17.15
17.16
18.1
18.2
18.3
12.5.1
12.5.2
POWER MANAGEMENT EVENT........................................................................................... 133
13.1.1
13.1.2
13.2.1
13.2.2
SERIALIZED IRQ.................................................................................................................... 141
WATCHDOG TIMER............................................................................................................... 144
GENERAL PURPOSE I/O....................................................................................................... 145
CONFIGURATION REGISTER............................................................................................... 147
SPECIFICATIONS .................................................................................................................. 189
18.3.1
18.3.2
18.3.3
18.3.4
18.3.5
Power Control Logic.......................................................................................................... 133
13.1.1.1.
Wake Up the System by Keyboard and Mouse ................................................................ 136
Resume Reset Logic......................................................................................................... 138
PWROK Generation.......................................................................................................... 138
Start Frame ....................................................................................................................... 141
IRQ/Data Frame................................................................................................................ 142
Stop Frame ....................................................................................................................... 143
GPIO Architecture............................................................................................................. 145
Access Channels .............................................................................................................. 145
Chip (Global) Control Register.......................................................................................... 147
Logical Device 0 (FDC)..................................................................................................... 154
Logical Device 1 (Parallel Port)......................................................................................... 158
Logical Device 2 (UART A) ............................................................................................... 159
Logical Device 3 (UART B) ............................................................................................... 160
Logical Device 5 (Keyboard Controller) ............................................................................ 161
Logical Device 6 (UART C)............................................................................................... 163
Logical Device 7 (GPIO3, GPIO4) .................................................................................... 164
Logical Device 8 (WDTO#, PLED, GPIO5, 6 & GPIO Base Address).............................. 166
Absolute Maximum Ratings .............................................................................................. 189
DC CHARACTERISTICS.................................................................................................. 189
AC CHARACTERISTICS .................................................................................................. 193
Logical Device 9 (GPIO1, GPIO2 and SUSLED) ....................................................... 170
Logical Device A (ACPI) ............................................................................................. 172
Logical Device B (Hardware Monitor) ......................................................................... 180
Logical Device C (PECI, SST) .................................................................................... 181
Logical Device D (UART D) ........................................................................................ 186
Logical Device E (UART E) ........................................................................................ 186
Logical Device F (UART F)......................................................................................... 188
KB Control Register (Logic Device 5, CR-F0)..........................................................................131
Port 92 Control Register (Default Value = 0x24)......................................................................132
PSON# Logic...........................................................................................................................134
AC Power Failure Resume ......................................................................................................135
Waken up by Keyboard events................................................................................................136
Waken up by Mouse events ....................................................................................................137
Power On / Off Timing .............................................................................................................193
AC Power Failure Resume Timing ..........................................................................................194
Clock Input Timing ...................................................................................................................199
PECI and SST Timing..............................................................................................................200
SMBus Timing .........................................................................................................................201
Normal Operation ..........................................................................................................134
-VII-
Publication Release Date: March 24, 2008
Revision 1.44