W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 5

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.
8.70
8.71
8.72
8.73
8.74
8.75
8.76
8.77
8.78
8.79
8.80
8.81
8.82
8.83
8.84
8.85
8.86
8.87
8.88
8.89
8.90
8.91
8.92
8.93
8.94
8.95
8.96
8.97
9.1
9.2
FLOPPY DISK CONTROLLER ................................................................................................. 85
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 1) ............................ 76
CPUTIN/PECI Temperature (Low Byte) Register - Index 51h (Bank 1) ............................. 76
CPUTIN Configuration Register - Index 52h (Bank 1)........................................................ 76
CPUTIN Hysteresis (High Byte) Register - Index 53h (Bank 1) ......................................... 77
CPUTIN Hysteresis (Low Byte) Register - Index 54h (Bank 1) .......................................... 77
CPUTIN Over-temperature (High Byte) Register - Index 55h (Bank1)............................... 77
CPUTIN Over-temperature (Low Byte) Register - Index 56h (Bank 1)............................... 78
SYSTIN/CPUTIN/PECI Temperature (High Byte) Register - Index 50h (Bank 2) .............. 78
SYSTIN/CPUTIN/PECI Temperature (Low Byte) Register – Index 51h (Bank 2) .............. 78
Reserved Registers – Index 52h (Bank 2).......................................................................... 79
Reserved Registers – Index 53h (Bank 2).......................................................................... 79
Reserved Registers – Index 54h (Bank 2).......................................................................... 79
Reserved Registers – Index 55h (Bank 2).......................................................................... 79
Reserved Registers – Index 56h (Bank 2).......................................................................... 79
Interrupt Status Register 3 – Index 50h (Bank 4) ............................................................... 79
SMI# Mask Register 4 – Index 51h (Bank 4) ...................................................................... 79
Reserved Register - Index 52h (Bank 4) ............................................................................ 80
BEEP Control Register 3 - Index 53h (Bank 4)................................................................... 80
SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4) .................................. 80
CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4).................................. 81
Reserved Registers - Index 56h (Bank 4)........................................................................... 81
Reserved Register - Index 57h-58h (Bank 4) ..................................................................... 81
Real Time Hardware Status Register I - Index 59h (Bank 4) ............................................. 81
Real Time Hardware Status Register II - Index 5Ah (Bank 4) ............................................ 82
Real Time Hardware Status Register III - Index 5Bh (Bank 4) ........................................... 83
Reserved Register - Index 5Ch - 5Fh (Bank 4) .................................................................. 83
Value RAM 2 ⎯ Index 50h-59h (Bank 5) ........................................................................... 83
Reserved Register - Index 50h - 57h (Bank 6) ................................................................... 84
FDC Functional Description ................................................................................................ 85
Register Descriptions.......................................................................................................... 94
FIFO (Data) .................................................................................................................................85
Data Separator............................................................................................................................86
Write Precompensation ...............................................................................................................86
Perpendicular Recording Mode...................................................................................................86
FDC Core ....................................................................................................................................87
FDC Commands .........................................................................................................................87
Status Register A (SA Register) (Read base address + 0) .........................................................94
Status Register B (SB Register) (Read base address + 1) .........................................................96
Digital Output Register (DO Register) (Write base address + 2).................................................97
Tape Drive Register (TD Register) (Read base address + 3) .....................................................97
Main Status Register (MS Register) (Read base address + 4) ...................................................98
Data Rate Register (DR Register) (Write base address + 4).......................................................99
FIFO Register (R/W base address + 5).....................................................................................100
Digital Input Register (DI Register) (Read base address + 7) ...................................................103
Configuration Control Register (CC Register) (Write base address + 7) ...................................104
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Publication Release Date: March 24, 2008
Revision 1.44