DP83816AVNG/NOPB National Semiconductor, DP83816AVNG/NOPB Datasheet - Page 48

• Manufacturer Part Number: DP83816AVNG/NOPB
• Description: IC MEDIA ACCESS CTRLR 144-LQFP
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG/NOPB

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• For Use With: DP83816-MAAP - BOARD EVALUATION DP83816
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83816AVNG; *DP83816AVNG/NOPB; DP83816AVNG

4.0 Register Set
4.2.10 Transmit Descriptor Pointer Register
This register points to the current Transmit Descriptor.
4.2.11 Transmit Configuration Register
This register defines the Transmit Configuration for DP83816. It controls such functions as Loopback, Heartbeat, Auto
Transmit Padding, programmable Interframe Gap, Fill & Drain Thresholds, and maximum DMA burst size.
31-2
Bit
Bit
1-0
31
30
29
28
Bit Name
Bit Name
TXDP
MLB
ATP
CSI
HBI
Offset: 0020h
Offset: 0024h
(Continued)
Tag: TXDP
Tag: TXCFG
Transmit Descriptor Pointer
The current value of the transmit descriptor pointer. When the transmit state machine is idle, software
must set TXDP to the address of a completed transmit descriptor. While the transmit state machine is
active, TXDP will follow the state machine as it advances through a linked list of active descriptors. If the
link field of the current transmit descriptor is NULL (signifying the end of the list), TXDP will not advance,
but will remain on the current descriptor. Any subsequent writes to the TXE bit of the CR register will
cause the transmit state machine to reread the link field of the current descriptor to check for new
descriptors that may have been appended to the end of the list. Transmit descriptors must be aligned on
an even 32-bit boundary in host memory (A1-A0 must be 0).
unused
Carrier Sense Ignore
Setting this bit to 1 causes the transmitter to ignore carrier sense activity, which inhibits reporting of CRS
status to the transmit status register. When this bit is 0 (default), the transmitter will monitor the CRS
signal during transmission and reflect valid status in the transmit status register and MIB counter block.
This bit must be set to enable full-duplex operation.
HeartBeat Ignore
Setting this bit to 1 causes the transmitter to ignore the heartbeat (CD) pulse which follows the packet
transmission and inhibits logging of TXSQEErrors in the MIB counter block. When this bit is set to 0
(default), the transmitter will monitor the heartbeat pulse and log TXSQEErrors to the MIB counter block.
This bit must be set to enable full-duplex operation
MAC Loopback
Setting this bit to a 1 places the DP83816 MAC into a loopback state which routes all transmit traffic to
the receiver, and disables the transmit and receive interfaces of the MII. A 0 in this bit allows normal MAC
operation. The transmitter and receiver must be disabled before enabling the loopback mode. (Packets
received during MLB mode will reflect loopback status in the receive descriptor’s
Automatic Transmit Padding
Setting this bit to 1 causes the MAC to automatically pad small (runt) transmit packets to the Ethernet
minimum size of 64 bytes. This allows driver software to transfer only actual packet data. Setting this bit
to 0 disables the automatic padding function, forcing software to control runt padding.
Access: Read Write
Access: Read Write
Size: 32 bits
Size: 32 bits
48
Description
Description
Hard Reset: 00000000h
Hard Reset: 00040102h
Soft Reset: 00000000h
Soft Reset: 00040102h
cmdsts.LBP
www.national.com
field.)