DP83816AVNG/NOPB National Semiconductor, DP83816AVNG/NOPB Datasheet - Page 87

• Manufacturer Part Number: DP83816AVNG/NOPB
• Description: IC MEDIA ACCESS CTRLR 144-LQFP
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG/NOPB

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• For Use With: DP83816-MAAP - BOARD EVALUATION DP83816
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83816AVNG; *DP83816AVNG/NOPB; DP83816AVNG

6.0 Power Management and Wake-On-LAN
6.1 Introduction
The DP83816 supports Wake-On-LAN (WOL) and the PCI
Power Management Specification version 1.1. These
features allow the device to enter a power saving mode,
and to signal the system to return to a normal operating
state when a wake event occurs. This section describes
the power management operation on the DP83816.
6.2 Definitions (for this document only)
Power State
• Power Management - a PCI specification that defines
• Wake event - An event that causes a PCI device in
• PME Enable (PMEEN) - bit 8 of the Power Manage-
• Sleep mode - A device is in sleep mode if it is pro-
• Wake-On-LAN mode - A device is in Wake-On-LAN
• PMEN (pin59) - this pin is similar in function to a sys-
• PME Status - bit 15 of PMCSR. When 1, indicates the
D3cold
D3cold
D3cold
D3hot
D3hot
D3hot
power-saving states of PCI devices and systems. A
spec-compliant device implements two PCI Configu-
ration registers to control and report status for its
Power Management function.
Power Management mode to signal the system.
ment Control/Status Register (PMCSR - offset 44h in
the PCI configuration space). Setting this bit to 1 al-
lows the device to assert the PMEN pin when it de-
tects a wake event.
grammed to a Power Management state other than
the fully operational state and is not allowed to signal
a wake event to the system. In this mode, the PME
Enable bit is 0.
(WOL) mode if it is programmed to a Power Manage-
ment state other than the fully operational state and is
allowed to signal a wake event to the system. In this
mode, the PME Enable bit is 1.
tem interrupt (INTAN pin). When asserted, it signals
the system that a wake event has occurred.
device detected a wake event. If PME Enable is also
set to 1, the device will assert PMEN whenever PME
Status is 1. Software writes a 1 to this bit to clear it.
D0
D1
D2
(SW sets to 0)
PME Enable
Don’t Care
Don’t Care
Don’t Care
Don’t Care
(PMEEN)
Off
On
Off
On
Table 6-1 Power Management Modes
Unconfigured
Unconfigured
Unconfigured
Configured
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Configured
Conditions
Wake
87
Power Management
6.3 Packet Filtering
When the PME Enable bit is set to 1, incoming packets are
filtered based on settings in the Receive Filter Control
Register (RFCR - offset 48h in operational registers) and
the Wake Command/Status Register (WCSR - offset 40h in
operational registers). In other words, a packet must pass
both filters to be accepted. This is a desirable feature in
WOL mode since it prevents non-wake packets from filling
the receive FIFO. However, it is not desirable in normal
operating mode since it will not allow non-wake packets
from being received. Therefore, the driver should ensure
that the PME Enable bit is set to 0 for normal operation.
6.4 Power Management
The Power Management Specification presents a low-level
hardware interface to PCI devices for the purpose of
saving power. The DP83816 supports power states D0,
D1, D2, D3hot, and D3cold as defined in the PCI Power
Management
increasing power reduction in the order they are listed.
Table 6-1 lists the different Power Management modes and
the methods of power reduction in DP83816 devices.
• Magic Packet: “A specific packet of information sent
• ACPI-compatible operating system - An operating
Normal
Mode
Sleep
Sleep
Sleep
Sleep
to remotely wake up a sleeping or powered off PC on
a network, it is handled in the LAN controller. The
Magic Packet must contain a specific data se-
quence which can be located anywhere within the
packet but must be preceded by a synchronization
stream. The packet must also meet the basic require-
ments for the LAN technology chosen (e.g. ethernet
frame). The specific data sequence consists of 16 du-
plications of the MAC address of the machine to be
awakened. The synchronization stream is defined as
6 bytes of FFh.”
system that takes advantage of the PCI Power Man-
agement interface. These include Windows 98 (when
installed with ACPI), Windows 2000, and Windows
ME (when installed with ACPI).
WOL
WOL
WOL
WOL
Specification.
May be Off
May be Off
May be Off
May be Off
PCICLK
On
On
Off
Off
Off
These
Physical Layer
states
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Cell
On
On
On
Off
Off
On
Off
Off
On
provide