DP83816AVNG/NOPB National Semiconductor, DP83816AVNG/NOPB Datasheet - Page 49

• Manufacturer Part Number: DP83816AVNG/NOPB
• Description: IC MEDIA ACCESS CTRLR 144-LQFP
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG/NOPB

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• For Use With: DP83816-MAAP - BOARD EVALUATION DP83816
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83816AVNG; *DP83816AVNG/NOPB; DP83816AVNG

4.0 Register Set
27-26
25-24
22-20
17-14
13-8
Bit
7-6
5-0
23
19
18
Bit Name
ECRETRY
MXDMA
DRTH
FLTH
IFG
(Continued)
Interframe Gap Time
This field allows the user to adjust the interframe gap time below the standard 9.6
960ns @100 Mb/s. The time can be programmed from 9.6
@100 Mb/s. Note that any value other than zero may violate the IEEE 802.3 standard. The formula for
the interframe gap is:
Reserved for NSC internal use only.
Must be written as a 00 otherwise. R/W
Excessive Collision Retry Enable
This bit enables automatic retries of excessive collisions. If set, the transmitter will retry the packet up to
4 excessive collision counts, for a total of 64 attempts. If the packet still does not complete successfully,
then the transmission will be aborted after the 64th attempt. If this bit is not set, then the transmit will be
aborted after the 16th attempt. Note that setting this bit will change how collisions are reported in the
status field of the transmit descriptor.
Max DMA Burst Size per Tx DMA Burst
This field sets the maximum size of transmit DMA data bursts according to the following table:
NOTE: The MXDMA setting value MUST not be greater than the TXCFG:FLTH (Tx Fill Threshold) value.
unused
Reserved for NSC internal use only.
Must be set to 1. Setting this bit to 0 selects a non-standard back-off algorithm that could increase the
likelihood of excessive collisions.
unused
Tx Fill Threshold
Specifies the fill threshold in units of 32 bytes. When the number of available bytes in the transmit FIFO
reaches this level, the transmit bus master state machine will be allowed to request the PCI bus for
transmit packet fragment reads. A value of 0 in this field will produce unexpected results and must not be
used.
Note: The FLTH value should be greater than the TXCFG:MXDMA value, but less than (txFIFOsize -
TXCFG:DRTH). In order to prevent FIFO pointer overlap internal to the device, the sum of the FLTH and
TXCFG:DRTH values should not exceed 2016 Bytes.
unused
Tx Drain Threshold
Specifies the drain threshold in units of 32 bytes. When the number of bytes in the FIFO reaches this
level (or the FIFO contains at least one complete packet) the MAC transmit state machine will begin the
transmission of a packet.
NOTE: In order to prevent a deadlock condition from occurring, the DRTH value should always be less
than (txFIFOsize - TXCFG:FLTH). A value of 0 in this field will produce unexpected results and must not
be used. Also, in order to prevent FIFO pointer overlap internal to the device, the sum of the DRTH and
TXCFG:FLTH values should not exceed 2016 Bytes.
9.6µs - 0.4(IFG[1:0]) µs @10 Mb/s and
960ns - 40(IFG[1:0])ns @100 Mb/s
000 = 128 32-bit words (512 bytes)
001 = 1 32-bit word (4 bytes)
010 = 2 32-bit words (8 bytes)
011 = 4 32-bit words (16 bytes)
100 = 8 32-bit words (32 bytes)
101 = 16 32-bit words (64 bytes)
110 = 32 32-bit words (128 bytes)
111 = 64 32-bit words (256 bytes)
49
Description
µ
s to 8.4
µ
s @10 Mb/s and 960ns to 840ns
µ
s @10 Mb/s and
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