PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 41

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
4
4.1
4.2
ADDRESS DECODING
PI7C8150A uses three address ranges that control I/O and memory transaction forwarding.
These address ranges are defined by base and limit address registers in the configuration
space. This chapter describes these address ranges, as well as ISA-mode and VGA
addressing support.
ADDRESS RANGES
PI7C8150A uses the following address ranges that determine which I/O and memory
transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from
the secondary bus to the primary bus:
Transactions falling within these ranges are forwarded downstream from the primary PCI
bus to the secondary PCI bus. Transactions falling outside these ranges are forwarded
upstream from the secondary PCI bus to the primary PCI bus.
No address translation is required in PI7C8150A. The addresses that are not marked for
downstream are always forwarded upstream.
I/O ADDRESS DECODING
PI7C8150A uses the following mechanisms that are defined in the configuration space to
specify the I/O address space for downstream and upstream forwarding:
This section provides information on the I/O address registers and ISA mode. Section 4.4
provides information on the VGA modes.
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the
command register in configuration space. All I/O transactions initiated on the primary bus
When PI7C8150A returns a target abort to the initiator, it sets the signaled target abort
bit in the status register corresponding to the initiator interface.
Two 32-bit I/O address ranges
Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges
Two 32-bit prefetchable memory address ranges
I/O base and limit address registers
The ISA enable bit
The VGA mode bit
The VGA snoop bit
Page 41 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A