PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 88

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
14.1.30
14.1.31
ARBITER CONTROL REGISTER – OFFSET 40h
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
Bit
10:9
15:11
Bit
24:16
25
31:26
Bit
0
1
15:2
Function
Test Mode For
All Counters at P
and S1
Reserved
Function
Arbiter Control
Priority of
Secondary
Interface
Reserved
Function
Memory Read
Flow Through
Enable
Park
Reserved
Type
R/O
R/O
Type
R/W
R/W
R/O
Type
R/W
R/W
R/O
Page 88 of 111
Description
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Description
Each bit controls whether a secondary bus master is assigned to the
high priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ_L[8:0]
respectively.
Bit 24 corresponds to S_REQ_L[8]
Bit 16 corresponds to S_REQ_L[0]
0: low priority
1: high priority
Reset to 0
Controls whether the secondary interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
Reserved. Returns 0 when read. Reset to 0.
Description
Controls ability to do memory read flow through
0: Disable flow through during a memory read transaction
1: Enable flow through during a memory read transaction
Reset to 0
Controls bus arbiter’s park function
0: Park to last master
1: Park to bridge
Reset to 0
Reserved. Returns 0 when read. Reset to 0
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A