NCN6004AFTBR2G ON Semiconductor, NCN6004AFTBR2G Datasheet - Page 27

• Manufacturer Part Number: NCN6004AFTBR2G
• Description: IC INTERFACE SAM/SIM DUAL 48TQFP
• Manufacturer: ON Semiconductor

Specifications of NCN6004AFTBR2G

• Applications: PC's, PDA's
• Interface: Microcontroller
• Voltage - Supply: 1.8 V ~ 5.5 V
• Package / Case: 48-TFQFP Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6004AFTBR2GOS; NCN6004AFTBR2GOS; NCN6004AFTBR2GOSTR

CLOCK DIVIDER
The main purpose of the built in clock generator is four
folds:
card ISO7816−3 and EMV specifications, the clock divider
is synchronized by the last flip flop, thus yielding a constant
50% duty cycle, regardless of the divider ratio.
In order to avoid any duty cycle out of the frequency smart
CLOCK_IN_A
CLOCK_IN_B
CARD_SEL
DC/DC BLOCK_A
DC/DC BLOCK_B
1. Adapts the voltage level shifter to cope with the
2. Provides a frequency division to adapt the Smart
3. Control the clock state according to the smart card
4. Provides an input clock re−routing to route the
PGM
CS
A2
A2
A1
A0
different voltages that might exist between the
MPU and the Smart Card
Card operating frequency from the external clock
source.
specification.
CLOCK_IN_A and CLOCK_IN_B signals to
either CRD_CLK_A or CRD_CLK_B output pins.
Figure 24. Simplified Frequency Divider and Programming Functions
CRD_VCC_A
CRD_VCC_B
1
2
CARD_A
CARD_B
3
CARD_A & CARD_B CLOCK
http://onsemi.com
CONTROL
NCN6004A
LOGIC
27
from the microprocessor to get the Duty Cycle window as
defined by the ISO7816−3 specification.
RESET fulfill the programming functions when both PGM
and CS are Low. The clock input stage (CLOCK_IN) can
handle a 40 MHz frequency maximum, the divider being
capable to provide an 1:8 ratio. Of course, the ratio must be
defined by the engineer to cope with the Smart Card
considered in a given application and, in any case, the output
clock (CRD_CLK_A and CRD_CLK_B) shall be limited to
20 MHz maximum when the system is considered to operate
over the full temperature range.
Consequently, the output CRD_CLK_A or CRD_CLK_B
frequency division can be delayed by eight CLOCK_IN
pulses and the microcontroller software must take this delay
into account prior to launch a new data transaction.
In addition, the NCN6004A adjusts the signal coming
The logic input pins CARD_SEL, A0, A1, PGM, I/O and
LEVEL SHIFTER
LEVEL SHIFTER
& CONTROL
& CONTROL
CRD_CLK_B
CRD_VCC_A
CRD_CLK_A
CRD_VCC_B