NCN6004AFTBR2G ON Semiconductor, NCN6004AFTBR2G Datasheet - Page 31

• Manufacturer Part Number: NCN6004AFTBR2G
• Description: IC INTERFACE SAM/SIM DUAL 48TQFP
• Manufacturer: ON Semiconductor

Specifications of NCN6004AFTBR2G

• Applications: PC's, PDA's
• Interface: Microcontroller
• Voltage - Supply: 1.8 V ~ 5.5 V
• Package / Case: 48-TFQFP Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6004AFTBR2GOS; NCN6004AFTBR2GOS; NCN6004AFTBR2GOSTR

signals must be independently controlled by the
microcontroller as depicted in Figure 31. The MUX_MODE
pin must be hardwired to VCC and it cannot be changed
side pins are not connected, the logic signals and the I/O line
being shared with CARD_A associated with the CRD_SEL
control bit: Figure 32. A key point is to make sure there is no
connection associated with the I/O_B pin since this pin is
internally shared with the I/O line transaction. The
CLK_IN_A and CLK_IN_B signals are independent and
can be routed to any of the card thanks to the built−in clock
multiplexer.
DATA I/O LEVEL SHIFTER
output signals, the I/O line being driven differently as
depicted in Figure 33. Since the NCN6004A can operate in
When the chip operates in the parallel mode, all the logic
In the multiplexed mode, the microprocessor CARD_B
The built in structure provides a level shifter on each card
CLOCK GEN.
CLOCK GEN.
CLOCK GEN.
CLOCK GEN.
Figure 32. Multiplexed Operation Wiring " MUX_MODE = High
Figure 31. Parallel Operation Wiring " MUX_MODE = Low
VCC
GND
MUX_MODE
MUX_MODE
CARD_SEL
CARD_SEL
CLK_IN_A
CLK_IN_B
CLK_IN_A
CLK_IN_B
RESET_A
RESET_B
RESET_A
RESET_B
I/O_A
I/O_B
C4_A
C8_A
I/O_A
I/O_B
C8_B
C4_B
C4_A
C8_A
C8_B
C4_B
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NCN6004A
13
15
10
12
19
16
17
18
44
13
15
10
11
12
19
16
17
18
44
11
9
5
9
5
31
CLOCK DIVIDER
CLOCK DIVIDER
MULTIPLEX &
during an operation of the chip. Beside this parameter, the
user must select to force or not the internal pull up resistors
as defined by the EN_RPU logic state.
MULTIPLEX &
either a multiplexed or parallel mode, provisions have been
made to route the I/O_A input pin to either CARD_A or
CARD_B.
structure with a 20 kW pull up resistor as shown Figure 33.
To achieve the 0.80 ms maximum rise time requested by the
EMV specifications, an accelerator circuit is added on both
side of each I/O line. These pulsed circuits yield boost
current to charge the stray capacitance, thus accelerating the
positive going slope of the I/O signal. On the other hand, the
active pull down NMOS device Q5 provides a low
impedance to ground during the battery up and DC/DC
start−up phase, avoiding any uncontrolled voltage spikes on
the I/O lines.
CONTROL
CONTROL
In both case, the I/O pins are driven by an open drain
LOGIC
LOGIC
CARD
CARD
BUFFERS
BUFFERS
BUFFERS
BUFFERS
CARD_A
CARD_B
BUFFER
BUFFER
CARD_A
BUFFER
BUFFER
CARD_B
BUFFER
BUFFER
BUFFER
BUFFER
CLK_A
CLK_B
CLK_A
CLK_B
I/O_A
I/O_B
I/O_A
I/O_B
30
31
23
22
21
24
37
38
39
40
30
31
23
22
21
24
37
38
39
40