NCN6004AFTBR2G ON Semiconductor, NCN6004AFTBR2G Datasheet - Page 6

• Manufacturer Part Number: NCN6004AFTBR2G
• Description: IC INTERFACE SAM/SIM DUAL 48TQFP
• Manufacturer: ON Semiconductor

Specifications of NCN6004AFTBR2G

• Applications: PC's, PDA's
• Interface: Microcontroller
• Voltage - Supply: 1.8 V ~ 5.5 V
• Package / Case: 48-TFQFP Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6004AFTBR2GOS; NCN6004AFTBR2GOS; NCN6004AFTBR2GOSTR

PIN DESCRIPTION (continued)
1. The external inductors shall preferably have the same values. Depending upon the power absorbed by the load, the inductor can range
Pin
18
19
20
21
22
23
24
25
26
27
from 10 mH to 47 mH. To achieve the highest yield, the inductor shall have an ESR < 1.0 W.
CRD_DET_A
CRD_RST_A
CRD_C8_A
CRD_C4_A
CRD_IO_A
PWR_GND
RESET_B
Symbol
I/O_B
L2_A
L1_A
INPUT/OUTPUT
INPUT/OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
POWER
INPUT
INPUT
Type
The signal present on this pin is translated to the RST pin of the external smart card #B.
The CS signal must be Low to valid the RESET function, regardless of the selected card.
Assuming the mP provides two independent lines to control the RESET pins, and
MUX_MODE = Low, the NCN6004A can control two cards simultaneously.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to
V
RESET_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to V
disconnected when EN_RPU = Low.
This pin carries the data transmission between an external microcontroller and the
external smart card #B.
A built−in bi−directional level translator adapts the signal flowing between the card and
the MCU. The level translator is enabled when CS = Low. The signal present on this pin
is latched when CS = High. Since a dedicated line is used to communicate the data
between the mP and the smart card, (assuming MUX_MODE = Low) the user can
activate the two channels simultaneously, assuming the mP provides a pair of I/O lines.
When MUX_MODE = High, this pin is internally disable, the pull up resistor is connected
to V
by I/O_A associated with CARD_SEL selection bit.
This pin senses the signal coming from the external smart card connector to detect the
presence of card #A. The polarity of the signal is programmable as Normally Open or
Normally Close switch. The logic signal will be activated when the level is either Low or
High, with respect to the polarity defined previously. By default, the input is Normally
Open. A built−in circuit prevents uncontrolled short pulses to generate an INT signal.
The digital filter eliminates pulse width below 50ms (see spec).
This pin controls the card #A C8 contact, according to the ISO7816 specifications. A
built−in level shifter is used to adapt the card and the mC, regardless of the power supply
voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL =L, or CS = H or
PGM = L, and resume to a transparent mode when card #A is selected and operates in
the transfer mode.The pin is hardwired to zero, the bias being provided by the V
supply, when either the V
startup time.
This pin controls the card #A C4 contact, according to the ISO7816 specifications. A
built−in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL = L, or CS = H, or
PGM = L, and resume to a transparent mode when card #A is selected and operates in
the transfer mode.
The pin is hardwired to zero, the bias being provided by the V
V
This pin is connected to the external smart card #A to support the RESET signal. A
built−in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL = Low, or when CS or
PGM returns to a High, and resume to a transparent mode when card #A is selected. The
pin is hardwired to zero, the bias being provided by the V
voltage drops below 2.7 V, or during the CRD_VCC_A startup time.
This pin carries the data serial connection between the external smart card #A and the
microcontroller. A built−in bidirectional level shifter is used to adapt the card and the
MCU, regardless of the power supply voltage of each signals.
This pin is biased by a pull up resistor connected to CRD_VCC_A. When CS = High, the
CRD_IO_A holds the previous I/O logic state and resume to a normal operation when this
pin is reactivated.
The pin is hardwired to zero, the bias being provided by the V
V
This pin carries the power current flow coming from the built in DC/DC converters. It is
associated with the external card # A. It must be connected to the system Ground and care
must be observed at PCB layout level to avoid the risk of spike voltages on the logic lines.
Connects one side of the external DC/DC converter inductor #A (Note 1).
Connects one side of the external DC/DC converter inductor #A (Note 1).
CC
CC
CC
, (regardless of the logic state of EN_RPU), and the access to card B takes place by
CC
voltage drops below 2.7 V, or during the CRD_VCC_A startup time.
voltage drops below 2.7 V, or during the CRD_VCC_A start−up time.
, (regardless of the logic state of EN_RPU), and the access to card B takes place
http://onsemi.com
NCN6004A
6
CC
voltage drops below 2.7 V, or during the CRD_VCC_A
Description
CC
CC
(EN_RPU = H) or
supply, when either the V
CC
CC
supply, when either the
supply, when either the
CC
CC