W83627EG Nuvoton Technology Corporation of America, W83627EG Datasheet - Page 127

• Manufacturer Part Number: W83627EG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

At the start of a command, the FIFO is always disabled, and command parameters must be sent based
upon the RQM and DIO bit settings in the Main Status Register. When the FDC enters the command
execution phase, it clears the FIFO off any data to ensure that invalid data are not transferred.
An overrun or underrun terminates the current command and data transfer. Disk writes complete the
current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the
remaining data so that the result phase may be entered.
DMA transfers are enabled by the specify command and are initiated by the FDC when the LDRQ pin is
activated during a data transfer command.
8.1.2
The function of the data separator is to lock onto incoming serial read data. When a lock is achieved,
the serial front-end logic in the chip is provided with a clock that is synchronized with the read data. The
synchronized clock, called the Data Window, is used to internally sample the serial data portion of the
bit cell, and the alternate state samples the clock portion. Serial-to-parallel conversion logic separates
the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The control logic generates RDD and RWD for every pulse input, and any data pulse input is
synchronized and then adjusted immediately by error adjustment. A digital integrator keeps track of the
speed changes in the input data stream.
8.1.3
The write precompensation logic minimizes bit shifts in the RDDATA stream from the disk drive.
Shifting of bits is a known phenomenon in magnetic media and depends on the disk media and the
floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known, so, depending on the pattern, the bit is shifted either early or late,
relative to the surrounding bits.
8.1.4
Data Separator
Write Precompensation
Perpendicular Recording Mode
15 Byte
2 Byte
8 Byte
2 x 8 μs - 1.5 μs = 14.5 μs
8 x 8 μs - 1.5 μs = 62.5 μs
15 x 8 μs - 1.5 μs = 118.5 μs
W83627EHF/EF, W83627EHG/EG
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