W83627EG Nuvoton Technology Corporation of America, W83627EG Datasheet - Page 171

• Manufacturer Part Number: W83627EG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 7, 6: These two bits are always read as logical 1. They can be written.
Bit 5: Direction control bit
port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and
fixed at zero.
Bit 4: A logical 1 allows an interrupt to occur when ACK# changes from low to high.
Bit 3: A logical 1 selects the printer.
Bit 2: A logical 0 starts the printer (50 microsecond pulse, minimum).
Bit 1: A logical 1 causes the printer to line-feed after a line is printed.
Bit 0: A logical 1 generates an active-high pulse for a minimum of 0.5μs to clock data into the printer.
Valid data must be present for a minimum of 0.5μs before and after the strobe pulse.
10.2.4 EPP Address Port
The address port is available only in EPP mode. Bit definitions are as follows:
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the
trailing edge of IOW# latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address
read cycle to be performed and the data to be output to the host CPU.
10.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. The bit definitions for each data port are the
same and as follows:
When this bit is logical 1, the parallel port is in input mode (read); when it is logical 0, the parallel
7
6
5
W83627EHF/EF, W83627EHG/EG
4
- 160 -
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7